According to one embodiment, a memory device includes a controller, and a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage using the verify step changing in a x-th loop (x is a natural number equal to or larger than 2). The controller is capable of changing a value of x, and indicates the value of x to the nonvolatile memory.
1. A memory device comprising:
a controller; and
a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage being used in the verify step and being changed in an x-th loop (x is a natural number equal to or larger than 2) based on a number of loop times and a voltage value of the erase pulse which differs in at least two loops,
wherein the controller is capable of changing a value of x, and indicates the value of x to the nonvolatile memory.
2. The memory device of claim 1 , wherein
the nonvolatile memory includes a register registering the value of x.
3. The memory device of claim 1 , wherein
the controller indicates a value of N as the value of x when Σ N i=1 (Verai×ti) exceeds a given value first, where Verai is the voltage value of the erase pulse in an i-th loop, and ti is a pulse width of the erase pulse in the i-th loop.
4. The memory device of claim 3 , wherein
the given value is informed from a host being connectable to the memory device or the nonvolatile memory.
5. The memory device of claim 3 , wherein
Verai and ti are informed from a host being connectable to the memory device or the nonvolatile memory.
6. The memory device of claim 1 , wherein
the nonvolatile memory has a default of x, and
the value of x is changed from the default.
7. The memory device of claim 1 , wherein
the erase-verify-read voltage is further changed in a y-th loop (y is a natural number equal to or larger than 3, and x<y), and
the controller is capable of changing a value of y, and indicates the value of y to the nonvolatile memory.
8. The memory device of claim 7 , wherein
the erase-verify-read voltage is changed from Vev1 to Vev2 in the x-th loop, and is changed from Vev2 to Vev3 in the y-th loop, where Vev1<Vev2<Vev3.
9. The memory device of claim 8 , wherein
Vev3=Vev1+2γ, and Vev2=Vev1+γ, where γ is any value which minimizes the cell stress.
10. The memory device of claim 1 , wherein
the voltage value of the erase pulse is changed every loop.
11. The memory device of claim 10 , wherein
Veraq=Vera_ini+(q−1)×α, where q is the number of loop times, Veraq is the voltage value of the erase pulse in a q-th loop, Vera_ini is an initial value of the voltage value of the erase pulse, and α is a steady value.
12. The memory device of claim 1 , wherein
the nonvolatile memory includes blocks, and the algorithm is executed every block.
13. The memory device of claim 1 , wherein
the controller is provided in a first chip, and the nonvolatile memory is provided in a second chip different from the first chip.
14. The memory device of claim 1 , wherein
the nonvolatile memory is a NAND memory.
15. The memory device of claim 1 , wherein
the memory device is a solid state drive (SSD).
16. A memory device comprising:
a controller; and
a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage being used in the verify step and being changed in an x-th loop (x is a natural number equal to or larger than 2),
wherein the controller indicates a value of N as a value of x when Σ N i=1 (Verai×ti) exceeds a given value first, where Verai is a voltage value of the erase pulse in an i-th loop, and ti is a pulse width of the erase pulse in the i-th loop.
17. The memory device of claim 16 , wherein
the nonvolatile memory includes a register registering the value of x.
18. The memory device of claim 16 , wherein
the controller is capable of changing a value of x, and indicates the value of x to the nonvolatile memory.
19. The memory device of claim 16 , wherein
the nonvolatile memory has a default of x, and
the value of x is changed from the default.
20. The memory device of claim 16 , wherein
the nonvolatile memory includes blocks, and the algorithm is executed every block.
21. A memory device comprising:
a controller; and
a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage being used in the verify step and being changed in an x-th loop (x is a natural number equal to or larger than 2) and in a y-th loop (y is a natural number equal to or larger than 3, and x<y),
wherein the erase-verify-read voltage is changed from Vev1 to Vev2 in the x-th loop, and is changed from Vev2 to Vev3 in the y-th loop, where Vev1<Vev2<Vev3, Vev3=Vev1+2γ, Vev2=Vev1+γ, and γ is any value which minimizes the cell stress.