Semiconductor memory device

1. A semiconductor memory device comprising:

a first bit line extending in a first direction;

a first source line extending in the first direction;

a first word line extending in a second direction crossing the first direction;

a first control line extending in the second direction;

a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line;

a second transistor including one end coupled to the first bit line; and

a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.

2. The device of claim 1 , wherein at writing, when the first memory cell is a writing-target cell, the second transistor is on and the third transistor is off.

3. The device of claim 1 , wherein at writing, when the first memory cell is a non-writing-target cell, the second transistor is off and the third transistor is on.

4. The device of claim 1 , wherein at reading, when the first memory cell is a reading-target cell, the second transistor is on and the third transistor is off.

5. The device of claim 1 , wherein at reading, when the first memory cell is a non-reading-target cell, the second transistor is off and the third transistor is on.

6. The device of claim 1 , further comprising a fourth transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.

7. The device of claim 6 , wherein the fourth transistor is arranged with the third transistor in the second direction.

8. The device of claim 1 , wherein:

at first writing for writing a first logical value in the first memory cell, a first voltage is applied to the first source line and a second voltage higher than the first voltage is applied to the first bit line; and

at second writing for writing a second logical value in the first memory cell, the first voltage is applied to the first source line and a third voltage lower than the first voltage is applied to the first bit line.

9. The device of claim 1 , further comprising:

a second bit line extending in the first direction;

a second source line extending in the first direction;

a second word line extending in the second direction;

a second control line extending in the second direction;

a second memory cell comprising a second variable resistance element and a fifth transistor, the fifth transistor including a gate coupled to the first word line, the second memory cell including one end coupled to the second bit line and another end coupled to the second source line;

a sixth transistor including one end coupled to the second bit line;

a seventh transistor including a gate coupled to the second control line, one end coupled to the second bit line, and another end coupled to the second source line;

an eighth transistor including one end coupled to the first source line and another end coupled to a first circuit; and

a ninth transistor including one end coupled to the second source line and another end coupled to a second circuit.

10. The device of claim 9 , wherein a gate of the eighth transistor and a gate of the ninth transistor are two different gates.

11. The device of claim 9 , wherein a gate of the eighth transistor and a gate of the ninth transistor are connected to a common word line.

12. A semiconductor memory device comprising:

a first bit line extending in a first direction;

a first source line extending in the first direction;

a first control line extending in a second direction crossing the first direction;

a first memory cell comprising a first variable resistance element and a first transistor, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; and

a second transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.

13. The device of claim 12 , wherein at writing, when the first memory cell is a writing-target cell, the second transistor is off.

14. The device of claim 12 , wherein at writing, when the first memory cell is a non-writing-target cell, the second transistor is on.

15. The device of claim 12 , wherein at reading, when the first memory cell is a reading-target cell, the second transistor is off.

16. The device of claim 12 , wherein at reading, when the first memory cell is a non-reading-target cell, the second transistor is on.

17. The device of claim 12 , further comprising a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.

18. The device of claim 17 , wherein the third transistor is arranged with the second transistor in the second direction.

19. The device of claim 12 , wherein

at first writing for writing a first logical value in the first memory cell, a first voltage is applied to the first source line and a second voltage higher than the first voltage is applied to the first bit line; and

at second writing for writing a second logical value in the first memory cell, the first voltage is applied to the first source line and a third voltage lower than the first voltage is applied to the first bit line.

20. The device of claim 12 , comprising

a second bit line extending in the first direction;

a second source line extending in the first direction;

a second control line extending in the second direction;

a second memory cell comprising a second variable resistance element and a fourth transistor, the second memory cell including one end coupled to the second bit line and another end coupled to the second source line;

a fifth transistor including a gate coupled to the second control line, one end coupled to the second bit line and another end coupled to the second source line;

a sixth transistor including one end coupled to the first source line and another end coupled to a first circuit; and

a seventh transistor including one end coupled to the second source line and another end coupled to a second circuit.