Patent Application

App. No. 15/265,037

Abstract

Claims (20)

1 . A clock interface with a propagation delay calibration function comprising:

a galvanic isolated transceiver configured to receive a 1PPS input signal from an upstream timing master and output a 1PPS output signal to a downstream timing slave;

a propagation delay measuring unit configured to receive the 1PPS input signal from the transceiver and measure a propagation delay of at least one of the 1PPS input signal and the 1PPS output signal during a propagation delay measuring period; and

a local PTP engine configured to receive the 1PPS input signal from the transceiver, compensate the 1PPS input signal using the propagation delay measured by the propagation delay measuring unit, and output the compensated 1PPS output signal,

wherein after the propagation delay measuring period starts, the clock interface sequentially:

pulls up a 1PPS input of the local PTP engine to a high level; disconnects a 1PPS input and a 1PPS output of the transceiver from the upstream timing master and the downstream timing slave, respectively; disconnects a chassis side ground of the transceiver from a chassis ground, and connects the chassis side ground of the transceiver to a digital ground inside the clock interface; and connects the IPPS input and the 1PPS output of the transceiver to the propagation delay measuring unit, respectively.

2 . The clock interface according to claim 1 , further comprising:

a trip circuit comprising a first buffer, a second buffer and a clamping resistance, wherein the first buffer is configured to buffer the 1PPS input signal from the transceiver and transmit it to the propagation delay measuring unit; the second buffer is configured to buffer the 1PPS input signal from the transceiver and transmit it to the local PTP engine; and the clamping resistance is located between the second buffer and the 1PPS input of the local PTP engine, for pulling up the 1PPS input of the local PTP engine to a high level during the propagation delay measuring period.

3 . The clock interface according to claim 2 , wherein the first buffer and the second buffer are same buffers.

4 . The clock interface according to claim 1 , further comprising:

an accelerated clock generator configured to generate a clock signal with a frequency higher than that of a 1PPS signal during the propagation delay measuring period, the clock signal or the 1PPS output signal outputted by the local PTP engine being selected and inputted into the propagation delay measuring unit.

5 . The clock interface according to claim 1 , wherein the downstream timing slave has an input open-circuit protection feature.

6 . The clock interface according to claim 1 , wherein the downstream timing slave does not have an input open-circuit protection feature, and the clock interface further comprises:

a parallel circuit configured to, at an early stage of the propagation delay measuring period, before the chassis side ground of the transceiver is disconnected from the chassis ground and the 1PPS input and the 1PPS output of the transceiver are connected to the propagation delay measuring unit, respectively, pull up the 1PPS output signal of the transceiver to a high level.

7 . The clock interface according to claim 6 , wherein the parallel circuit is further configured to, at a late stage of the propagation delay measuring period, before the chassis side ground of the transceiver is connected to the chassis ground and the 1PPS input and the 1PPS output of the transceiver are disconnected from the propagation delay measuring unit, respectively, pull down the 1PPS output signal of the transceiver to a low level.

8 . The clock interface according to claim 1 , wherein before completion of the propagation delay measurement period, the clock interface sequentially: pulls down the 1PPS input of the local PTP engine to a low level; disconnects the 1PPS input and the 1PPS output of the transceiver from the propagation delay measuring unit, respectively; connects the chassis side ground of the transceiver to the chassis ground and disconnects the chassis side ground from the digital ground within the clock interface; and connects the 1PPS input and the 1PPS output of the transceiver to the upstream timing master and the downstream timing slave, respectively.

9 . The clock interface according to claim 1 , further comprising:

a switch set comprising a first switch, a second switch, a third switch, a fourth switch, and a fifth switch,

wherein a fixed terminal of the first switch is connected to the 1PPS input of the transceiver, a first switching terminal of the first switch is connected to the upstream timing master, a second switching terminal of the first switch is connected to a fixed terminal of the third switch, a fixed terminal of the second switch is connected to the 1PPS output of the transceiver, a first switching terminal of the second switch is connected to the downstream timing slave, a second switching terminal of the second switch is connected to a first switching terminal of the fourth switch, a fixed terminal of the third switch is connected to a second switching terminal of the first switch, a first switching terminal of the third switch floats, a second switching terminal of the third switch is connected to the 1PPS output of the local PTP engine, a fixed terminal of the fourth switch is connected to the propagation delay measuring unit, a first switching terminal of the fourth switch is connected to a second switching terminal of the second switch, a second switching terminal of the fourth switch floats, a fixed terminal of the fifth switch is connected to the chassis side ground of the transceiver, a first switching terminal of the fifth switch is connected to the chassis ground, and a second switching terminal of the fifth switch is connected to the digital ground.

10 . The clock interface according to claim 1 , wherein the transceiver is a RS-422 transceiver.

Assignments (8)