Semiconductor memory device including a sense amplifier on a semiconductor substrate, a memory cell including a capacitor and a transistor including conductive lines electrically connected to the sense amplifier

1. A semiconductor memory device comprising:

a semiconductor substrate;

a sense amplifier on the semiconductor substrate;

a memory cell array including a memory cell above the sense amplifier, the memory cell including a capacitor and a first transistor, the capacitor including a first electrode and a second electrode, the first transistor including a first current path and a first control electrode controlling an on/off of the first current path, the first current path including a first terminal and a second terminal, the first terminal being electrically connected to the first electrode;

a first conductive line electrically connected to the second terminal and extending along an upper surface of the semiconductor substrate in a first direction, the first conductive line being electrically connected to the sense amplifier;

a second transistor including a second current path and a second control electrode controlling an on/off of the second current path, the second current path including a third terminal and a fourth terminal, and the third terminal being electrically connected to the first conductive line; and

a second conductive line electrically connected to the fourth terminal,

wherein the second current path is provided between the first and second conductive lines, the second conductive line is electrically connected to a power source having a predetermined potential, and the first conductive line is set to the predetermined potential by turning on the second current path,

wherein the second transistor is disposed above the sense amplifier and apart from the semiconductor substrate, and

wherein the first current path comprises a first semiconductor layer, and the second current path comprises a second semiconductor layer.

2. The device of claim 1 , wherein

the first and second semiconductor layers are oxide semiconductor layers.

3. The device of claim 2 , wherein

each of the oxide semiconductor layers includes indium oxide, gallium oxide and zinc oxide.

4. The device of claim 1 , wherein

the first and second semiconductor layers are semiconductor pillars.

5. The device of claim 1 , further comprising:

a selector on the semiconductor substrate, the selector being electrically connected between the first conductive line and the sense amplifier.

6. The device of claim 1 , wherein

the second electrode is a part of a plate electrode covering the memory cell array.

7. The device of claim 1 , wherein

the second electrode is set to a fixed potential.

8. The device of claim 1 , wherein

the first conductive line is set to the predetermined potential in a read operation.

9. The device of claim 1 , wherein

the second conductive line extends along the upper surface of the semiconductor substrate in a second direction crossing the first direction.

10. The device of claim 1 , wherein

the sense amplifier is disposed directly under the memory cell array.

11. The device of claim 1 , wherein

the first current path comprises the first semiconductor layer between the capacitor and the first conductive line.

12. The device of claim 1 , wherein

the first current path extends in a direction crossing the upper surface of the semiconductor substrate.

13. The device of claim 1 , wherein

the second current path extends in a direction crossing the upper surface of the semiconductor substrate.

14. The device of claim 1 , wherein

the second transistor is disposed side by side with the first transistor in the first direction.

15. The device of claim 1 , wherein

the second current path extends along the upper surface of the semiconductor substrate.

16. The device of claim 1 , wherein

the first transistor is disposed above the capacitor.

17. The device of claim 1 , wherein

the capacitor is disposed above the first transistor.