Memory device
A memory device according to one embodiment includes a first interconnection, a second interconnection, a charge storage portion provided between the first interconnection and the second interconnection, a tunnel film provided between the first interconnection and the charge storage portion, and a block film. the charge storage portion is capable of accumulating an electron. The tunnel film includes a fine particulate layer that including conductive fine particulates satisfying the Coulomb blockade condition, a first tunnel insulating layer provided between the first interconnection and the fine particulate layer, and a second tunnel insulating layer provided between the fine particulate layer and the charge storage portion. The block film is provided between the charge storage portion and the second interconnection. The block film has an energy structure in which no concave portion with an energy barrier lower than energy barriers on both sides thereof is present.
1. A memory device comprising:
a first interconnection;
a second interconnection;
a charge storage portion provided between the first interconnection and the second interconnection, the charge storage portion being capable of accumulating an electron;
a tunnel film provided between the first interconnection and the charge storage portion, the tunnel film including:
a fine particulate layer including conductive fine particulates satisfying the Coulomb blockade condition,
a first tunnel insulating layer provided between the first interconnection and the fine particulate layer, and
a second tunnel insulating layer provided between the fine particulate layer and the charge storage portion; and
a block film provided between the charge storage portion and the second interconnection, the block film having an energy structure in which no concave portion with an energy barrier lower than energy barriers on both sides thereof is present.
2. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer,
a second insulating layer disposed between the charge storage portion and the first insulating layer, and
a third insulating layer disposed between the first insulating layer and the second interconnection, and
energy of the first insulating layer is higher than energy of the second insulating layer and energy of the third insulating layer.
3. The memory device according to claim 1 , further comprising a semiconductor layer provided between the first interconnection and the tunnel film, energy of the semiconductor layer being higher than energy of the first interconnection.
4. The memory device according to claim 1 , wherein
a writing operation is carried out by applying a writing voltage between the first interconnection and the second interconnection to allow electrons to tunnel through the tunnel film and to cause the electrons to be blocked by the block film, and
a reading operation is carried out by applying a reading voltage between the first interconnection and the second interconnection to allow electrons that have tunneled through the tunnel film to pass through the block film, the reading voltage having the same polarity as the writing voltage and being higher than the writing voltage.
5. The memory device according to claim 1 , wherein
in an erased state in which electrons have been removed from the charge storage portion, when a reading voltage is applied, electrons that have passed through the tunnel film have energy that is higher than the highest energy barrier in the block film.
6. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer, and
a second insulating layer disposed between the charge storage portion and the first insulating layer, energy of the second insulating layer being lower than energy of the first insulating layer, and
when an effective oxide film thickness of the overall tunnel film is T, an effective oxide film thickness of the overall block film is T B , an effective oxide film thickness of the second insulating layer is T 7 , an energy barrier of the first insulating layer is H B , an elementary charge is q, and a reading voltage is Vread, the following expression is satisfied:
q×V read×( T+T 7 )/( T+T B )≧ H B .
7. The memory device according to claim 1 , wherein when a writing voltage is applied, energy of electrons that have passed through the tunnel film is lower than the highest energy barrier in the block film.
8. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer, and
a second insulating layer disposed between the charge storage portion and the first insulating layer, energy of the second insulating layer being lower than energy of the first insulating layer, and
when an effective oxide film thickness of the overall tunnel film is T, an effective oxide film thickness of the overall block film is T B , an effective oxide film thickness of the second insulating layer is T 7 , an energy barrier of the first insulating layer is H B , an elementary charge is q, and a writing voltage is Vwrite, the following expression is satisfied:
q×V write×( T+T 7 )/( T+T B )< H B .
9. The memory device according to claim 1 , wherein
in a written state in which electrons have been accumulated in the charge storage portion, when a reading voltage is applied, energy of electrons that have passed through the tunnel film is higher than the highest energy barrier in the block film.
10. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer, and
a second insulating layer disposed between the charge storage portion and the first insulating layer, energy of the second insulating layer being lower than energy of the first insulating layer, and
when an effective oxide film thickness of the overall tunnel film is T, an effective oxide film thickness of the overall block film is T B , an effective oxide film thickness of the first tunnel insulating layer is T 3 , an effective oxide film thickness of the second insulating layer is T 7 , an energy barrier of the first insulating layer is H B , an elementary charge is q, and a reading voltage is Vread, the following expression is satisfied:
q×V read×( T+T 7 )/( T+T B )≧ H B +q× 0.18 V× T ×( T B −T 7 )/[ T 3 ×T B ].
11. The memory device according to claim 1 , wherein
the highest energy barrier in the tunnel film is higher than the highest energy barrier in the block film.
12. The memory device according to claim 1 , wherein
when electrostatic energy of one electron on the conductive fine particulate is ΔE, an elementary charge is q, and an effective oxide film thickness of the first tunnel insulating layer is T 3 , the following expression is satisfied:
q× 15 MV/cm× T 3 ≧ΔE≧ 5×26 meV.
13. The memory device according to claim 1 , wherein
the conductive fine particulate is silicon microcrystal having a grain size of 3 nm or less.
14. The memory device according to claim 1 , wherein
the first tunnel insulating layer is a silicon oxide layer having a thickness of 2 nm or less, and
the second tunnel insulating layer is a silicon oxide layer having a thickness of 2 nm or less.
15. The memory device according to claim 1 , wherein
the charge storage portion is a continuous film made from metal, or, includes a plurality of metal dots disposed in a dispersed manner.
16. The memory device according to claim 1 , wherein
the charge storage portion includes a dangling bond or a trap level formed by a defect.
17. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer, and
a second insulating layer disposed between the charge storage portion and the first insulating layer, energy of the second insulating layer being lower than energy of the first insulating layer, and
the second insulating layer includes hafnium oxide, hafnium silicate with a silicon concentration of 30% or less, or silicon nitride.
18. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer, and
a second insulating layer disposed between the charge storage portion and the first insulating layer, energy of the second insulating layer being lower than energy of the first insulating layer, and
the second insulating layer is a hafnium oxide layer having a physical film thickness of 2 nm or less, a hafnium silicate layer having a physical film thickness of 2 nm or less, or a silicon nitride layer having a physical film thickness of 3 nm or less.
19. The memory device according to claim 1 , wherein
the block film includes
a first insulating layer, and
a second insulating layer disposed between the charge storage portion and the first insulating layer, energy of the second insulating layer being lower than energy of the first insulating layer, and
the first insulating layer includes silicon oxide, aluminum oxide, lanthanum oxide, or lanthanum aluminum silicate.
20. The memory device according to claim 1 , further comprising a semiconductor layer provided between the tunnel film and the charge storage portion, energy of the semiconductor layer being higher than energy of the charge storage portion.