Trench contact resistance reduction
A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.
1. A method of forming a semiconductor device, the method comprising:
forming a source/drain over a semiconductor substrate;
epitaxially growing a single sacrificial layer directly in contact with only the source/drain to protect the source/drain from subsequent etches;
forming an inter-level dielectric (ILD) layer contacting the single sacrificial layer;
forming a first portion of trenches that extend through the ILD layer at an oblique angle with respect to the semiconductor substrate, and into a first section of the single sacrificial layer such that the single sacrificial layer remains in contact with an entire upper surface of the source/drain;
removing a second section of the single sacrificial layer to expose the entire upper surface of the source/drain and to create a second portion of the trenches which extends laterally beyond sidewalls of the first portion of the trenches; and
filling the first and second portions of the trenches with a plurality of conducting materials extending laterally over all the exposed portions of the source/drain.
2. The method of claim 1 , further comprising forming a gate structure on the semiconductor substrate.
3. The method of claim 2 , further comprising forming spacers adjacent the gate structure.
4. The method of claim 3 , wherein the trenches run transversely to a longitudinal axis of the gate structure.
5. The method of claim 4 , wherein the sacrificial layer is germanium (Ge).
6. The method of claim 5 , wherein the sacrificial layer is prevented from extending over the gate structure.
7. The method of claim 1 , wherein one of the plurality of conducting materials contacts an entire inner surface of the ILD layer.
8. The method of claim 1 , wherein the plurality of conducting materials are three conducting materials.
9. The method of claim 8 , wherein the first conducting material is titanium (Ti), the second conducting material is titanium nitride (TiN), and the third conducting material is Tungsten (W).
10. The method of claim 9 , wherein the first conducting material contacts the source/drain.