Method and circuit for adjusting the frequency of a clock signal

1. A method for adjusting an oscillator clock frequency, the method comprising:

applying a first control value to a first oscillator;

applying a second control value, different from the first control value, to a second oscillator;

measuring a frequency of each of the first and second oscillators;

determining, by interpolation, a new first control value depending on the frequencies measured, on the first and second control values, and on a desired frequency;

applying the new first control value to the first oscillator; and

determining, by interpolation, a corrected frequency measurement of the second oscillator, the corrected frequency measurement being dependent on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the second control value, the corrected frequency measurement being used as a frequency measurement of the second oscillator for determining the new first control value.

2. The method according to claim 1 , further comprising a calibration phase including:

applying the third control value to each of the first and second oscillators; and

measuring the frequency deviation between the frequencies of the first and second oscillators when subjected to the third control value.

3. The method according to claim 1 , further comprising a calibration phase including:

applying a minimum control value to each of the first and second oscillators;

measuring a first frequency deviation between the first and second oscillators when subjected to the minimum control value;

applying a maximum control value to each of the first and second oscillators;

measuring a second frequency deviation between the first and second oscillators when subjected to the maximum control value; and

determining a slope deviation between response curves of the first and second oscillators depending on a difference between the first and second frequency deviations and on a difference between the minimum and maximum control values, the slope deviation being used to determine, by interpolation, the corrected frequency measurement.

4. The method according to claim 1 , wherein the corrected frequency measurement is determined based on a frequency deviation measured between the first and second oscillators when subjected to a minimum control value, and on the minimum control value.

5. The method according to claim 1 , wherein the measured frequency of the first oscillator, when subjected to the third control value, corresponds to the desired frequency.

6. The method according to claim 5 , further comprising a calibration phase including:

determining the third control value, and

measuring the frequency of the second oscillator when subjected to the third control value.

7. The method according to claim 1 , wherein each frequency measurement of the first oscillator or the second oscillator includes counting a number of cycles of the respective oscillator during a period of a synchronization signal.

8. The method according to claim 7 , wherein the synchronization signal is supplied by a communication interface.

9. The method according to claim 8 , further comprising supplying a signal at the frequency of the first oscillator at an output of the first oscillator as a clock signal of a device conforming to the USB 2.0 standard, the frequency of the first oscillator being equal to 6 MHz with an error margin of ±90 KHz, or to 48 MHz with an error margin of ±120 KHz.

10. The method according to claim 1 , wherein the determination of the new first control value includes:

determining a first difference between the measured frequencies of the first and second oscillators;

determining a second difference between the desired frequency and the measured frequency of one of the first and second oscillators;

dividing the first difference by a difference between the first and second control values applied to the first and second oscillators, to obtain a frequency pitch;

dividing the second difference by the frequency pitch to obtain a correction value; and

adding the correction value to the first control value to obtain the new first control value.

11. The method according to claim 10 , wherein the difference between the first and second control values is a fixed value, a new second control value is determined depending on the new first control value or on the correction value to keep the difference in control values at the fixed value.

12. A frequency adjusting circuit for adjusting the frequency of an oscillator to a desired frequency, the frequency adjusting circuit comprising:

first and second oscillators each having a frequency and being adjustable by a control value,

the frequency adjusting circuit being configured to implement a method including:

applying a first control value to the first oscillator;

applying a second control value, different from the first control value, to the second oscillator;

measuring a frequency of each of the first and second oscillators;

determining, by interpolation, a new first control value depending on the frequencies measured, on the first and second control values, and on a desired frequency;

applying the new first control value to the first oscillator; and

determining, by interpolation, a corrected frequency measurement of the second oscillator, the corrected frequency measurement being dependent on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the second control value, the corrected frequency measurement being used as a frequency measurement of the second oscillator for determining the new first control value.

13. The frequency adjusting circuit according to claim 12 , wherein each of the first and second oscillators comprises a ring oscillator including a plurality of delay circuits that can be activated separately based on which of the first and second control values is applied.

14. The frequency adjusting circuit according to claim 12 , configured to perform a calibration phase including:

applying the third control value to each of the first and second oscillators; and

measuring the frequency deviation between the frequencies of the first and second oscillators when subjected to the third control value.

15. The frequency adjusting circuit according to claim 12 , configured to perform a calibration phase including:

applying a minimum control value to each of the first and second oscillators;

measuring a first frequency deviation between the first and second oscillators when subjected to the minimum control value;

applying a maximum control value to each of the first and second oscillators;

measuring a second frequency deviation between the first and second oscillators when subjected to the maximum control value; and

determining a slope deviation between response curves of the first and second oscillators depending on a difference between the first and second frequency deviations and on a difference between the minimum and maximum control values, the slope deviation being used to determine, by interpolation, the corrected frequency measurement.

16. The frequency adjusting circuit according to claim 12 , wherein the frequency adjusting circuit is further configured to determine the corrected frequency measurement based on a frequency deviation measured between the first and second oscillators when subjected to a minimum control value, and on the minimum control value.

17. The frequency adjusting circuit according to claim 12 , wherein the measured frequency of the first oscillator, when subjected to the third control value, corresponds to the desired frequency.

18. The frequency adjusting circuit according to claim 17 , configured to perform a calibration phase including:

determining the third control value, and

measuring the frequency of the second oscillator when subjected to the third control value.

19. The frequency adjusting circuit according to claim 12 , wherein each frequency measurement of the first oscillator or the second oscillator includes counting a number of cycles of the respective oscillator during a period of a synchronization signal.

20. The frequency adjusting circuit according to claim 19 , wherein the synchronization signal is supplied by a communication interface.

21. The frequency adjusting circuit according to claim 20 , configured to supply a signal at the frequency of the first oscillator at an output of the first oscillator as a clock signal of a device conforming to the USB 2.0 standard, the frequency of the first oscillator being equal to 6 MHz with an error margin of ±90 KHz, or to 48 MHz with an error margin of ±120 KHz.

22. The frequency adjusting circuit according to claim 12 , wherein the frequency adjusting circuit is further configured to determine the new first control value by:

determining a first difference between the measured frequencies of the first and second oscillators;

determining a second difference between the desired frequency and the measured frequency of one of the first and second oscillators;

dividing the first difference by a difference between the first and second control values applied to the first and second oscillators, to obtain a frequency pitch;

dividing the second difference by the frequency pitch to obtain a correction value; and

adding the correction value to the first control value to obtain the new first control value.

23. The frequency adjusting circuit according to claim 22 , wherein the difference between the first and second control values is a fixed value, the frequency adjusting circuit being further configured to determine a new second control value depending on the new first control value or on the correction value to keep the difference in control values at the fixed value.

24. A USB 2.0 device comprising:

an interface circuit configured to receive a data signal conforming to the USB 2.0 standard, and

a frequency adjusting circuit comprising first and second oscillators each having a frequency and being adjustable by a control value,

the frequency adjusting circuit being configured to implement a method including:

applying a first control value to the first oscillator;

applying a second control value, different from the first control value, to the second oscillator;

measuring a frequency of each of the first and second oscillators;

determining, by interpolation, a new first control value depending on the frequencies measured, on the first and second control values, and on a desired frequency;

applying the new first control value to the first oscillator; and

determining, by interpolation, a corrected frequency measurement of the second oscillator, the corrected frequency measurement being dependent on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the second control value, the corrected frequency measurement being used as a frequency measurement of the second oscillator for determining the new first control value.

25. The USB 2.0 device according to claim 24 , wherein an interface circuit supplies the frequency adjusting circuit with a synchronization signal.