APD focal plane arrays with backside vias
An avalanche photodiode (APD) array with reduced cross talk comprises, in the illustrative embodiment, a 2D array of Geiger-mode APDs, wherein a via is formed through the backside (substrate) of each APD in the array.
1. An article comprising a plurality of avalanche photodiodes (APDs), each APD comprising:
a substrate layer having a first surface and a second surface, wherein, in operation, input light is received at the first surface of the substrate layer and propagates toward the second surface thereof;
a buffer layer abutting the second surface of the substrate layer;
a via extending from the first surface of the substrate layer and passing at least partially through the substrate layer towards the second surface thereof; and
active device layers, wherein, at least some of the vias of the article are filled with transparent epoxy.
2. The article of claim 1 wherein the substrate layer comprises InP.
3. The article of claim 1 wherein a minimum diameter of each via is at least as large as an active region of the APDs, and wherein each via is superposed with respect to the active region of a respective APD and aligned therewith.
4. The article of claim 1 further comprising a read-out integrated circuit, wherein the read-out integrated circuit (ROIC) and the APDs are electrically coupled.
5. The article of claim 4 further comprising a plurality of indium bumps, wherein each indium bump is used to couple an APD to the ROIC.
6. The article of claim 4 wherein each indium bump aligns with a respective via.
7. The article of claim 1 wherein the APDs are Geiger-mode APDs.
8. The article of claim 1 wherein at least some of the vias pass completely through the substrate layer.
9. The article of claim 7 wherein at least some of the vias pass completely through the substrate layer.
10. An article comprising a plurality of avalanche photodiodes (APDs), each APD comprising:
a substrate layer having a first surface and a second surface, wherein, in operation, input light is received at the first surface of the substrate layer and propagates toward the second surface thereof;
a buffer layer abutting the second surface of the substrate layer;
a via extending from the first surface of the substrate layer and passing at least partially through the substrate layer towards the second surface thereof; and
active device layers, wherein:
the APDs are organized in a 2D array, each APD defining a pixel and wherein the 2D array is characterized by a pixel pitch, and wherein a maximum diameter of the vias is about 75% of the pixel pitch and wherein a minimum diameter of the vias is at least as large as a diameter of an active region of each pixel.
11. The article of claim 10 wherein the APDs are Geiger-mode APDs.
12. The article of claim 11 wherein at least some of the vias pass completely through the substrate layer.
13. The article of claim 10 wherein a minimum diameter of each via is at least as large as an active region of the APDs, and wherein each via is superposed with respect to the active region of a respective APD and aligned therewith.
14. The article of claim 10 further comprising a plurality of indium bumps, wherein each indium bump aligns with a respective via and is used to couple a respective APD to a read-out integrated circuit (ROIC).
15. An article comprising a plurality of Geiger-mode avalanche photodiode (GmAPDs), each GmAPD comprising:
a substrate layer having a first surface and a second surface, wherein, in operation, input light is received at the first surface of the substrate layer and propagates toward the second surface thereof;
a buffer layer abutting the second surface of the substrate layer;
a via passing through the substrate layer and the buffer layer; and
an active region,
wherein the GmAPDs are organized in a 2D array, each GmAPD defining a pixel and wherein the 2D array is characterized by a pixel pitch, and wherein a maximum diameter of the via of each of the GmAPDs in the 2D array is about 75% of the pixel pitch and wherein a minimum diameter of the via of each of the GmAPDs is at least as large as a diameter of the active region of each pixel.
16. The article of claim 15 wherein at least some of the vias are filled with a transparent material.
17. The article of claim 15 wherein the substrate layer comprises InP.
18. The article of claim 15 further comprising a read-out integrated circuit, wherein the read-out integrated circuit (ROIC) and the GmAPDs are electrically coupled to one another.
19. The article of claim 15 wherein each GmAPDs further comprises an absorption layer having a first surface abutting the buffer layer.
20. The article of claim 19 further comprising an electrical passivation layer, which is not opaque and is disposed in the via and extending between the second surface of the substrate layer and the first surface of the absorption layer.
21. The article of claim 15 further comprising a cap layer comprising a multiplication region and a diffused region, wherein the active region of the each GmAPD contains the multiplication region and a portion of the diffused region, and wherein a central axis of the via aligns with the center of the active region.