IP Library Granted Patent US 9,929,086
Granted Patent B2
US 9,929,086 · App. 15/270,497 · Granted Mar 27, 2018

Semiconductor device

Inventors: Kazuo Tomita (Kawasaki, JP); Keiichi Yamada (Kawasaki, JP)
Assignee: Renesas Electronics Corporation
H01L23/5223H01L23/5222H01L23/5286H01L23/585H01L27/016H01L27/0248H01L27/0805H01L28/40H01L28/75H01L28/86H01L28/60H01L28/82H01L2924/0002
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Quick Facts
Patent No.
US 9,929,086
App. No.
15/270,497
Granted
Mar 27, 2018
Kind
B2
Abstract

In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween. The lower electrode (LEL), the dielectric film (DEC), and the upper electrodes (UEL) constitute MIM capacitors (MCA). One of the upper electrodes (UEL) and another upper electrode (UEL) that are adjacent to each other are arranged at an equal distance (D 1 ), without the guard ring being interposed therebetween. The upper electrodes (UEL) positioned on the outermost periphery and the guard ring (GR) positioned outside those upper electrodes UEL are arranged at a distance equal to the distance (D 1 ) from each other.

Claims (21)

1. A semiconductor integrated circuit device comprising:

a semiconductor substrate;

a plurality of MIM capacitors disposed over the semiconductor substrate, each MIM capacitor including a lower electrode, a dielectric film, and an upper electrode; and

a guard ring arranged to continuously surround all of the plurality of MIM capacitors without branching,

wherein the plurality of MIM capacitors are arranged spaced apart from each other by a prescribed distance,

wherein the guard ring is arranged spaced apart from an outermost MIM capacitor by a distance which is the same as the prescribed distance, and

wherein the guard ring is electrically connected to the lower electrode of the outermost MIM capacitor through a metal layer disposed above the guard ring.

2. A semiconductor integrated circuit device according to claim 1 ,

wherein a planar pattern of each of the plurality of MIM capacitors is a square.

3. A semiconductor integrated circuit device according to claim 2 ,

wherein the prescribed potential is ground potential.

4. A semiconductor integrated circuit device according to claim 1 ,

wherein a planar pattern of each of the plurality of MIM capacitors is a rectangle.

5. A semiconductor integrated circuit device according to claim 1 ,

wherein the guard ring is formed on the same layer as the upper electrode.

6. A semiconductor integrated circuit device according to claim 1 ,

wherein the guard ring is formed by a titanium nitride film.

7. A semiconductor integrated circuit device according to claim 1 ,

wherein the prescribed distance is 1.6 μm.

8. A semiconductor integrated circuit device according to claim 1 ,

wherein the guard ring is fixed to a prescribed potential.

Assignments (1)
CHANGE OF ADDRESS Recorded Dec 7, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044742/0288 →
Continuity (2)
Continuation 14238474
Related Publication 20170012032A1 · Jan 12, 2017