IP Library Granted Patent US 9,837,960
Granted Patent B2
US 9,837,960 · App. 15/272,695 · Granted Dec 5, 2017

Oscillation circuit

Inventor: Kosuke Takada (Chiba, JP)
Assignee: SII SEMICONDUCTOR CORPORATION
H03B5/1234H02M3/07H03B5/1271H03K3/0231H03L7/00
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Quick Facts
Patent No.
US 9,837,960
App. No.
15/272,695
Granted
Dec 5, 2017
Kind
B2
Abstract

Provided is an oscillation circuit that can limit a maximum value and a minimum value of a frequency even when some troubles are caused in a V/I conversion circuit. The oscillation circuit includes a current controlled oscillator configured to oscillate based on an input current, and a current limiting circuit configured to: compare the input current with a first constant current and with a second constant current; limit, when the input current reaches the first constant current, a maximum current value of the input current with a transistor arranged on a path of the input current; and limit, when the input current is lowered to the second constant current, a minimum current of the input current through addition of current on the path of the input current by a transistor arranged in parallel with the path of the input current.

Claims (29)

1. An oscillation circuit, comprising:

a current source circuit configured to generate a second current based on a first current flowing through a first current path between a power supply terminal and a current input terminal; and

a current controlled oscillator configured to oscillate based on the second current, the current source circuit comprising:

a first PMOS transistor in the first current path, and including a gate and a drain connected to each other;

a second PMOS transistor forming a current mirror circuit with the first PMOS transistor, the second PMOS transistor configured to cause the second current to flow therethrough;

a third PMOS transistor forming a current mirror circuit with the first PMOS transistor;

a constant current source connected to a drain of the third PMOS transistor; and

a fourth PMOS transistor configured to limit a current value of the first current, and including a gate controlled by a voltage of the drain of the third PMOS transistor.

2. An oscillation circuit according to claim 1 , wherein the fourth PMOS transistor is connected to the power supply terminal and to the current input terminal in the first current path and is configured to limit a maximum current value of the first current.

3. An oscillation circuit according to claim 1 , wherein the fourth PMOS transistor is in second current path between the current input terminal and a ground terminal and is connected to the current input terminal and the ground terminal and is configured to limit a minimum current value of the first current.

4. An oscillation circuit according to claim 2 , further comprising:

a fifth PMOS transistor forming a current mirror circuit with the first PMOS transistor;

a constant current source connected to a drain of the fifth PMOS transistor; and

a sixth transistor in a second current path between the current input terminal and a ground terminal,

wherein the sixth transistor is configured to limit a minimum current value of the first current.

5. An oscillation circuit according to claim 1 , further comprising a V/I conversion circuit configured to output a predetermined current based on a predetermined voltage,

wherein an output of the V/I conversion circuit is connected to the current input terminal.

6. An oscillation circuit according to claim 1 , further comprising:

a phase/frequency comparator circuit configured to receive a clock signal and output of the current controlled oscillator;

a charge pump circuit configured to receive output of the phase/frequency comparator circuit;

a capacitor connected to an output of the charge pump circuit;

an NMOS transistor including a drain connected to the current input terminal, and a gate configured to receive an output of the charge pump circuit; and

a resistor connected to a source of the NMOS transistor.

7. An oscillation circuit, comprising:

a current controlled oscillator configured to oscillate based on an input current; and

a current limiting circuit including a maximum current source, a minimum current source, an input terminal and a ground terminal, and configured to:

compare the input current with a first constant current and with a second constant current;

when the input current reaches the first constant current, limit a maximum current value of the input current with a transistor having a gate connected to the maximum current source in a path of the input current between the input terminal and the ground terminal; and

when the input current is lowered to the second constant current, limit a minimum current of the input current through addition of current on the path of the input current by a transistor having a gate connected to the minimum current source and in parallel with the path of the input current.

Assignments (3)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2016
From: TAKADA, KOSUKE
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 039836/0121 →
Priority Claims (1)
JP 2015-194570 · Sep 30, 2015 · national
Continuity (1)
Related Publication 20170093334A1 · Mar 30, 2017