IP Library Granted Patent US 9,812,422
Granted Patent B2
US 9,812,422 · App. 15/273,549 · Granted Nov 7, 2017

Embedded die-down package-on-package device

Inventors: Toong Erh Ooi (Butterworth, MY); Bok Eng Cheah (Bayan Lepas, MY); Nitesh Nimkar (Chandler, AZ)
Assignee: Intel Corporation
H01L24/82H01L21/486H01L21/4846H01L21/4857H01L23/498H01L23/49822H01L23/49827H01L23/50H01L23/5383H01L23/5384H01L23/5389H01L25/105H01L25/50H01L24/19H01L24/24H01L24/73H01L2224/04105H01L2224/12105H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/821H01L2224/82005H01L2224/82039H01L2224/82345H01L2225/0651H01L2225/06568H01L2225/1035H01L2225/1058H01L2225/1076H01L2924/12042H01L2924/1517H01L2924/15311H01L2924/15331H01L2924/181H01L2924/1815H01L2924/18162H05K1/185H05K3/4682H05K2201/10674
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Quick Facts
Patent No.
US 9,812,422
App. No.
15/273,549
Granted
Nov 7, 2017
Kind
B2
Abstract

An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.

Claims (22)

1. A method comprising:

disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate;

disposing a spacer layer on the sacrificial substrate, the spacer layer comprising an opening to accommodate the die on the sacrificial substrate;

forming a build-up carrier adjacent a device side of the die, wherein the build-up carrier comprises:

a plurality of alternating layers of conductive material and dielectric material, and

dielectric material embedding a portion of a thickness dimension of the die and defining a gradation between the device side of the die and a backside of the die, the gradation comprising a plurality of carrier contact points configured for mounting the build-up carrier to the substrate; and

after forming the build-up carrier, separating the die and the build-up carrier from the sacrificial substrate and the spacer layer.

2. The method of claim 1 , wherein the spacer layer has a thickness equivalent to a thickness of the gradation and the opening in the spacer layer comprises an opening to accommodate the dielectric material to embed a portion of the thickness dimension of the die.

3. The method of claim 2 , wherein forming the build-up carrier comprises forming the plurality of carrier contact points on the spacer layer.

4. The method of claim 3 , wherein the plurality of carrier contact points are configured for connection of the build-up carrier to a printed circuit board.

5. A method comprising:

disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate;

forming a build-up carrier adjacent the device side of the die, wherein the build-up carrier comprises:

a plurality of alternating layers of conductive material and dielectric material, and

dielectric material embedding a portion of a thickness dimension of the die and defining a first gradation between the device side of the die and a backside of the die, the first gradation comprising a plurality of carrier contact points configured for mounting the build-up carrier to the substrate; and

separating the die and the build-up carrier from the sacrificial substrate,

wherein forming the build-up carrier comprises:

patterning a penultimate layer of the plurality of conductive layers and forming a spacer layer on the patterned penultimate layer, the spacer layer comprising an opening to accommodate an ultimate layer of the plurality of conductive layers, the spacer layer having a thickness equivalent to a thickness of a second gradation;

patterning the ultimate layer of the plurality of conductive layers; and

after forming the build-up carrier, removing the spacer layer.

6. The method of claim 5 , wherein forming the build-up carrier comprises disposing dielectric material on the patterned ultimate layer of the plurality of conductive layers.

7. The method of claim 5 , patterning the penultimate layer of the plurality of conductive layers comprises patterning the penultimate layer into the second plurality of carrier contact points configured for connection of the build-up carrier to a secondary device or package.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2017
From: OOI, TOONG ERH; CHEAH, BOK ENG; NIMKAR, NITESH
To: INTEL CORPORATION
Reel/Frame 042511/0942 →
Continuity (2)
Division 13852876 · Mar 28, 2013
Related Publication 20170012020A1 · Jan 12, 2017