IP Library Granted Patent US 10,205,664
Granted Patent B2
US 10,205,664 · App. 15/279,267 · Granted Feb 12, 2019

System and method for routing

Inventors: Nathan Farrington (Arcadia, CA); Chiang Yeh (Sierra Madre, CA); Bhaskar Chowdhuri (San Diego, CA)
Assignee: Rockley Photonics Limited
H04L45/745H04L45/08H04L45/34H04L45/50H04L47/628H04L49/3009
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Quick Facts
Patent No.
US 10,205,664
App. No.
15/279,267
Granted
Feb 12, 2019
Kind
B2
Abstract

A system and method for routing. A packet includes a stack of one or more headers, such as a stack of Multiprotocol Label Switching headers, that determines the path that the packet will take, through a sequence of switches, from its source to its destination. Each header in the stack contains an output port identifier that identifies an output port of a corresponding switch in the path. Each switch, upon receiving the packet, removes the first header to form a shortened packet, and routes the shortened packet to the output port identified by the output port identifier.

Claims (49)

1. A system for processing input data packets, the system having a plurality of output ports and comprising:

a state machine comprising:

a state register; and

combinational logic,

the state machine being configured to:

receive an input data packet; and

remove from the input data packet a header containing an output port identifier identifying an output port of the plurality of output ports, to form a shortened packet;

the system being configured to output the shortened packet through the identified output port,

the system further comprising an input first-in, first-out structure (input FIFO), the state machine being configured to receive the input data packet from the input FIFO,

the system further comprising an output first-in, first-out structure (output FIFO), the state machine being configured to feed the shortened packet to the output FIFO,

wherein the state machine is configured to process input Ethernet data packets, each input Ethernet data packet including an Ethernet header and one or more Multiprotocol Label Switching (MPLS) headers, and wherein the header is the first MPLS header of the one or more MPLS headers,

wherein the state machine is further configured to:

remove from an input Ethernet data packet an MPLS header, to form a shortened packet; and

feed the shortened packet to the output FIFO,

when an Ethertype field of the Ethernet header has a value of hexadecimal 8847; and

feed the input Ethernet data packet to the output FIFO,

when an Ethertype field of the Ethernet header does not have a value of hexadecimal 8847.

2. The system of claim 1 , wherein the state machine is configured to receive the input Ethernet data packet from the input FIFO one input data word at a time.

3. The system of claim 2 , wherein the length of each input data word is 256 bits.

4. The system of claim 2 , wherein the state machine is configured to feed to the output FIFO a sequence of output data words, each of the output data words consisting of a part of a first input data word received from the input FIFO and a part of a second input word received from the input FIFO after the first input data word.

5. The system of claim 4 , further comprising a demultiplexer to convert, at the input of the system, a first data stream carrying the input Ethernet data packets, to a second data stream, having a greater width and a lower clock speed than the first data stream,

the system being configured to feed the second data stream to the input FIFO.

6. The system of claim 5 , wherein the input FIFO is an asynchronous FIFO.

7. A system for processing input data packets, the system having a plurality of output ports and comprising:

a state machine comprising:

a state register; and

combinational logic,

the state machine being configured to:

receive an input data packet; and

remove from the input data packet a header containing an output port identifier identifying an output port of the plurality of output ports, to form a shortened packet;

the system being configured to output the shortened packet through the identified output port,

the system further comprising an input first-in, first-out structure (input FIFO), the state machine being configured to receive the input data packet from the input FIFO,

the system further comprising an output first-in, first-out structure (output FIFO), the state machine being configured to feed the shortened packet to the output FIFO,

wherein the state machine is configured to process input Ethernet data packets, each input Ethernet data packet including an Ethernet header and one or more Multiprotocol Label Switching (MPLS) headers, and wherein the header is the first MPLS header of the one or more MPLS headers,

wherein the state machine is configured to receive the input Ethernet data packet from the input FIFO one input data word at a time,

wherein the state machine is configured to feed to the output FIFO a sequence of output data words, each of the output data words consisting of a part of a first input data word received from the input FIFO and a part of a second input word received from the input FIFO after the first input data word,

the system further comprising a demultiplexer to convert, at the input of the system, a first data stream carrying the input Ethernet data packets, to a second data stream, having a greater width and a lower clock speed than the first data stream,

the system being configured to feed the second data stream to the input FIFO,

wherein the state machine is configured, when the first MPLS header of the Ethernet packet is not the only MPLS header of the Ethernet packet, upon receiving a final input data word of the packet containing the end of a data packet, to

combine the final input data word with a part of the previous input data word to form an output data word,

when the length of valid data in the final input data word is not greater than the length of the first MPLS header, and

combine a part of the final input data word with a part of the previous input data word to form an output data word; and

form a final output data word from the remainder of the final input data word,

when the length of valid data in the final input data word is less than the length of the first MPLS header.

8. The system of claim 1 , wherein the outputting of the shortened packet through the identified output port comprises extracting the output port identifier from a portion of the first MPLS header.

9. The system of claim 8 , wherein the portion of the first MPLS header is the MPLS label portion of the first MPLS header.

10. The system of claim 1 , wherein the state machine is further configured to

remove from the input Ethernet data packet a codeword,

when the Ethertype field of the Ethernet header has a value of hexadecimal 8847 and the first MPLS header is the only MPLS header of the Ethernet packet.

Assignments (10)
SECURITY INTEREST Recorded Mar 19, 2023
From: ROCKLEY PHOTONICS LIMITED
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS COLLATERAL AGENT
Reel/Frame 063287/0879 →
RELEASE OF PATENT SECURITY INTEREST - SUPER SENIOR INDENTURE - REEL/FRAME 061768/0082 Recorded Mar 19, 2023
From: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS COLLATERAL AGENT
To: ROCKLEY PHOTONICS LIMITED
Reel/Frame 063264/0416 →
RELEASE OF SECURITY INTEREST - REEL/FRAME 060204/0749 Recorded Mar 19, 2023
From: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS COLLATERAL AGENT
To: ROCKLEY PHOTONICS LIMITED
Reel/Frame 063264/0333 →
SECURITY INTEREST - SUPER SENIOR INDENTURE Recorded Oct 25, 2022
From: ROCKLEY PHOTONICS LIMITED
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS COLLATERAL AGENT
Reel/Frame 061768/0082 →
SECURITY INTEREST Recorded May 27, 2022
From: ROCKLEY PHOTONICS LIMITED
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS COLLATERAL AGENT
Reel/Frame 060204/0749 →
RELEASE OF SECURITY INTEREST Recorded May 18, 2022
From: SILICON VALLEY BANK
To: ROCKLEY PHOTONICS LIMITED
Reel/Frame 059948/0387 →
RELEASE OF SECURITY INTEREST Recorded May 18, 2022
From: KREOS CAPITAL V (UK) LIMITED
To: ROCKLEY PHOTONICS LIMITED
Reel/Frame 060116/0136 →
SECURITY INTEREST Recorded May 26, 2017
From: ROCKLEY PHOTONICS LIMITED
To: KREOS CAPITAL V (UK) LIMITED
Reel/Frame 042517/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2017
From: FARRINGTON, NATHAN; YEH, CHIANG; CHOWDHURI, BHASKAR
To: ROCKLEY PHOTONICS LIMITED
Reel/Frame 041790/0498 →
SECURITY INTEREST Recorded Jan 27, 2017
From: ROCKLEY PHOTONICS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 041108/0640 →
Continuity (2)
Provisional Application 62234451 · Sep 29, 2015
Related Publication 20170093717A1 · Mar 30, 2017