Memory device

1. A memory device comprising:

a semiconductor column extending above a substrate;

a first conductive layer on a first side of the semiconductor column;

a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer;

a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column;

a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer;

a fifth conductive layer adjacent the first conductive layer on the first side of the semiconductor column and between the first and third conductive layers;

a sixth conductive layer on the second side of the semiconductor column, opposite to the fifth conductive layer; and

a bit line connected to the semiconductor column, wherein during reading in which a positive voltage is applied to the bit line:

a first voltage is applied to the first conductive layer and a second voltage is applied to the second conductive layer;

a third voltage is applied to the third conductive layer and a fourth voltage is applied to the fourth conductive layer;

a fifth voltage is applied to the fifth conductive layer and a sixth voltage is applied to the sixth conductive layer;

the first voltage and the third voltage are higher than each of the second voltage and the sixth voltage;

the fifth voltage is higher than the first, second, third, fourth and sixth voltages; and

the third voltage is higher than the first voltage.

2. The memory device according to claim 1 , wherein the second, fourth, and sixth voltages are negative voltages.

3. The memory device according to claim 1 , wherein the second and fourth voltages are negative voltages, and the sixth voltage is a positive voltage.

4. The memory device according to claim 1 , wherein the semiconductor column has a first pillar portion that faces the first and third conductive layers and extends above the substrate, and a second pillar portion that faces the second and fourth conductive layers and extends above the substrate, the first and second pillar portions being electrically isolated from each other.

5. The memory device according to claim 4 , further comprising:

a first transistor that controls an electrical connection and disconnection between the bit line and the first pillar portion; and

a second transistor that controls an electrical connection and disconnection between the bit line and the second pillar portion, wherein

during the reading in which the positive voltage is applied to the bit line, the first transistor is turned on and the second transistor is turned off.

6. The memory device according to claim 1 , further comprising:

a second semiconductor column extending above the substrate and connected to the bit line, wherein

the first and third conductive layers extend parallel to a surface of the substrate to face a first side of the second semiconductor column.

7. The memory device according to claim 6 , further comprising:

seventh and eighth conductive layers on a second side of the second semiconductor column, opposite to the first and third conductive layers, respectively.

8. The memory device according to claim 7 , wherein

during the reading in which the positive voltage is applied to the bit line, negative voltages are applied to the seventh and eighth conductive layers.

9. The memory device according to claim 7 , wherein

during the reading in which the positive voltage is applied to the bit line, a negative voltage is to the seventh conductive layer and a positive voltage less than the first voltage is applied to the eighth conductive layer.