IP Library Granted Patent US 10,891,892
Granted Patent B2
US 10,891,892 · App. 15/280,554 · Granted Jan 12, 2021

Display device

Inventors: Tetsuo Fukami (Hyogo, JP); Masahiro Ishii (Hyogo, JP)
Assignee: Panasonic Liquid Crystal Display Co., Ltd.
G09G3/2085G09G3/3677G09G3/3696H01L27/3223H01L27/3272H01L27/3276G09G2300/0426G09G2300/0814G09G2310/0218
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Quick Facts
Patent No.
US 10,891,892
App. No.
15/280,554
Granted
Jan 12, 2021
Kind
B2
Abstract

A display device comprises: selector transistors in each of which one of conductive electrodes is connected to each of ends of gate lines, the selector transistor being divided into a plurality; selection signal supplying wirings each of which is provided in each block, and connected to each control electrode of the selector transistors corresponding to the block; gate voltage supplying wirings that are commonly connected to the other conductive electrode of each of the selector transistors; a gate driver that sequentially supplies a gate voltage to the gate voltage supplying wirings while supplying a control voltage to the selection signal supplying wiring in order to on or off the selector transistor, and a light shielding part that is disposed between at least the two adjacent blocks.

Claims (33)

1. A display device, comprising:

a plurality of data lines extending in a first direction;

a plurality of groups, each group having a plurality of gate lines extending in a second direction, wherein the plurality of gate lines for each group are adjacent in the first direction;

a plurality of blocks, each block including:

a plurality of selector transistors and each of the plurality of selector transistors includes:

a first conductive electrode connected to an end of a corresponding gate line of the plurality of gate lines,

a second conductive electrode, and

a control electrode,

wherein each block among the plurality of blocks corresponds to a group among the plurality of the groups;

a plurality of selection signal supplying wirings, each of which is connected to the control electrode of each of the plurality of selector transistors for a corresponding block of the plurality of blocks;

a plurality of gate voltage supplying wirings each of which is connected to the second conductive electrode of one of the plurality of selector transistors in each of the groups;

a gate driver that sequentially supplies a gate voltage to the plurality of gate voltage supplying wirings and supplies a control voltage to the plurality of selection signal supplying wirings to turn on or off one or more of the plurality of selector transistors; and

a dummy transistor having a control electrode and being disposed between two adjacent blocks among the plurality of blocks,

wherein the plurality of blocks include a first block and a second block next to the first block,

the first conductive electrodes of the plurality of selector transistors included in the first block are connected to the ends of the corresponding gate lines respectively,

the first conductive electrodes of the plurality of selector transistors included in the second block are connected to the ends of the corresponding gate lines respectively,

the dummy transistor is disposed between one of the plurality of selector transistors in the first block and one of the plurality of selector transistors in the second block,

the control electrode of each of the plurality of selector transistors included in the first block and the control electrode of the dummy transistor disposed between the first block and the second block are integrally formed, and

the control electrode of the dummy transistor disposed between the first block and the second block is electrically isolated from and spaced apart from the control electrode of each of the plurality of selector transistors included in the second block.

2. The display device according to claim 1 , wherein the first block and the second block among the plurality of blocks are sequentially arranged in a scanning direction, and a light shielding part is disposed between a selector transistor connected to a gate line scanned last in the first block and a selector transistor connected to a gate line scanned first in the second block.

3. The display device according to claim 1 , wherein the control electrodes for each of the plurality of selector transistors included in a block among the plurality of blocks are integrally formed.

4. The display device according to claim 1 , further comprising a light shielding part that is an extended part of the control electrode of a selector transistor among the plurality of selector transistors.

5. The display device according to claim 1 , wherein the dummy transistor includes a first conductive electrode and a second conductive electrode, wherein each of the plurality of selection signal supplying wirings is not connected to the first conductive electrode and the second conductive electrode of the dummy transistor, and wherein each of the plurality of gate voltage supplying wirings is not connected to the first conductive electrode and the second conductive electrode of the dummy transistor.

6. The display device according to claim 1 , wherein a dummy signal supplying wiring through which a dummy signal is supplied is connected to a first conductive electrode of each dummy transistor, and a capacitance is connected to a second conductive electrode of each dummy transistor.

7. The display device according to claim 1 , wherein a first conductive electrode of the dummy transistor is connected to a corresponding gate voltage supplying wiring among the plurality of gate voltage supplying wirings, and a capacitance is connected to the second conductive electrode of the dummy transistor.

8. The display device according to claim 1 , wherein the plurality of selector transistors for each block are adjacent in the first direction and at least partially overlap when viewed in the first direction.

9. The display device according to claim 1 , further comprising:

a second dummy transistor having a control electrode and being disposed between two adjacent blocks among the plurality of blocks, wherein

the plurality of blocks include a third block next to the second block, the first conductive electrodes of the plurality of selector transistors included in the third block being connected to the ends of the corresponding gate lines respectively,

the first block, the second block, and the third block are arranged in this order,

the second dummy transistor is disposed between one of the plurality of selector transistors in the second block and one of the plurality of selector transistors in the third block,

the control electrode of each of the plurality of selector transistors included in the second block and the control electrode of the second dummy transistor disposed between the second block and the third block are integrally formed, and

the control electrode of the second dummy transistor disposed between the second block and the third block is electrically isolated from and spaced apart from the control electrode of each of the plurality of selector transistors included in the third block.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2017
From: FUKAMI, TETSUO; ISHII, MASAHIRO
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 043528/0195 →
Priority Claims (1)
JP 2015-195072 · Sep 30, 2015 · national
Continuity (1)
Related Publication 20170092182A1 · Mar 30, 2017