Memory device that performs sensing operation during a bit line pre-charge operation to determine adjustment to the bit line charging voltage

1. A memory device comprising:

memory cells;

word lines that are each connected to gates of a plurality of the memory cells;

bit lines that are each connected to a plurality of the memory cells; and

a control circuit configured to perform a determination operation on the memory cells,

wherein during the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged to a target voltage using a bit line charge voltage, which is adjusted based on a result of a first sensing operation that is performed on the first bit line during the charging of the first bit line to the target voltage, and a second sensing operation is performed on the first bit line after completion of the charging of the first bit line to the target voltage to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.

2. The device according to claim 1 , wherein the bit line charge voltage is adjusted to a first voltage if the first sensing operation generates a first result and adjusted to a second voltage higher than the first voltage if the first sensing operation generates a second result.

3. The device according to claim 2 , further comprising:

a sense amplifier circuit including a bit line control circuit, a plurality data latches, and a wiring between the bit line control circuit and the data latches, wherein

the wiring is at a low voltage level if the first sensing operation generates the first result and the wiring is at a high voltage level if the first sensing operation generates the second result.

4. The device according to claim 3 , wherein the bit line control circuit includes

a first transistor between a first voltage source and a bit line charging node, and

a second transistor between a second voltage source and the bit line charging node,

wherein the second voltage source supplies voltage at a lower level than the first voltage source, and

wherein the first transistor is turned off and the second transistor is turned on, if the wiring is at the low voltage level, and the first transistor is turned on and the second transistor is turned off, if the wiring is at the high voltage level.

5. The device according to claim 4 , wherein the bit line control circuit further includes

a third transistor between the first transistor and the bit line charging node, the third transistor being turned on and a gate voltage supplied to the second transistor being lowered to cause an adjustment of the bit line charge voltage.

6. The device according to claim 1 , wherein the control circuit is configured to perform the determination operation during a verify operation.

7. The device according to claim 1 , wherein the control circuit is configured to perform the determination operation during a read operation.

8. A memory device comprising:

memory cells including a first memory cell;

word lines that are each connected to gates of a plurality of the memory cells;

bit lines that are each connected to a plurality of the memory cells; and

a control circuit configured to perform a bit line pre-charge operation during a determination operation on the memory cells,

wherein during the bit line pre-charge operation on a first bit line connected to the first memory cell,

the first bit line is initially charged using an initial bit line charge voltage, and

before completion of the bit line pre-charge operation, a sensing operation is performed on the first bit line to determine a new bit line charge voltage based on a result of the sensing operation, and then the bit line pre-charge operation is completed using the new bit line charge voltage.

9. The device according to claim 8 , wherein the initial bit line charge voltage is applied during a first period of the bit line pre-charge operation and the new bit line charge voltage is applied during a second period of the bit line pre-charge operation that is after the first period.

10. The device according to claim 9 , wherein the new bit line charge voltage is greater than the initial bit line charge voltage if the sensing operation indicates that the first bit line is below a first voltage level.

11. The device according to claim 9 , wherein the new bit line charge voltage is less than or equal to the initial bit line charge voltage if the sensing operation indicates that the first bit line is above a first voltage level.

12. The device according to claim 8 , wherein the controller is configured to perform another sensing operation on the first bit line after completion of the bit line charge operation.

13. The device according to claim 12 , wherein said another sensing operation on the first bit line is carried out to determine whether or not the first memory cell has a threshold voltage that is higher than a reference voltage.

14. A memory device comprising:

memory cells;

a bit line that is connected to a plurality of the memory cells;

a sense amplifier configured to perform a sense operation on the bit line; and

a control circuit configured to control the sense amplifier during a bit line pre-charge operation on the memory cells, wherein

the sense amplifier includes a bit line control circuit and the bit line control circuit includes a first transistor between a first voltage source and a bit line charging node, and a second transistor between a second voltage source and the bit line charging node, the second voltage source supplying voltage at a lower level than the first voltage source, and

during the bit line pre-charge operation that includes a first period and a second period after the first period:

a first voltage is applied to the second transistor in the first period and a second voltage lower than the first voltage is applied to the second transistor in the second period, and

a third voltage is applied to the first transistor at the beginning of the first period, while a fourth voltage higher than the third voltage is applied to the first transistor during a sensing operation that is carried out during the first period, and a fifth voltage higher than the third voltage and lower than the fourth voltage is applied to the first transistor in the second period.

15. The memory device according to claim 14 , wherein the sense amplifier further includes data latches and a wiring between the bit line control circuit and the data latches, and the bit line control circuit further includes a third transistor between the first voltage source and the second transistor, the third transistor being controlled according to a voltage level of the wiring.

16. The memory device according to claim 15 , wherein the bit line control circuit further includes a sense node, and a voltage level of the sense node that is sensed during the sensing operation causes the voltage level of the wiring to be at a high level or a low level.

17. The memory device according to claim 16 , wherein the control circuit is configured to perform another sensing operation after the bit line pre-charge operation.

18. The memory device according to claim 16 , wherein said another sensing operation is performed in connection with a verify operation.

19. The memory device according to claim 16 , wherein said another sensing operation is performed in connection with a read operation.