IP Library Granted Patent US 10,275,156
Granted Patent B2
US 10,275,156 · App. 15/280,725 · Granted Apr 30, 2019

Managing solid state drive defect redundancies at sub-block granularity

Inventors: Anand S. Ramalingam (Beaverton, OR); Jawad B. Khan (Cornelius, OR); Pranav Kalavade (San Jose, CA)
Assignee: Intel Corporation
G06F3/0608G06F3/0652G06F3/0679G11C16/0483G11C16/16G11C16/3445G06F3/064G06F3/0658G06F3/0659
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Quick Facts
Patent No.
US 10,275,156
App. No.
15/280,725
Granted
Apr 30, 2019
Kind
B2
Abstract

Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.

Claims (43)

1. A system comprising:

a compute subsystem;

a communications interface coupled to the compute subsystem; and

a memory device coupled to the communications interface, the memory device including:

a non-volatile memory to initiate an erase operation for a block of the non-volatile memory in response to an erase command, wherein the block is to include a plurality of sub-blocks; and

a non-volatile memory controller communicatively coupled to the non-volatile memory, the non-volatile memory controller to track a failure of the erase operation for the block on an individual sub-block basis, wherein the non-volatile memory controller is to:

transfer, in response to an indication that the erase operation for the block failed, an erase status enhanced command to the non-volatile memory to obtain an identification made from the erase operation for the block of each individual sub-block in a first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block; and

receive, from the non-volatile memory, a response to the erase status enhanced command including the identification made from the erase operation for the block of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

2. The system of claim 1 , wherein the non-volatile memory controller is to permit use of a second subset of the plurality of sub-blocks that successfully erased during the erase operation for the block.

3. The system of claim 1 , wherein the non-volatile memory controller is to prevent use of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

4. The system of claim 1 , wherein a first field of the response to the erase status enhanced command is one byte of data and a second field of the response to the erase status enhanced command is a variable number of bytes or a fixed number of bytes.

5. The system of claim 1 , wherein the non-volatile memory controller is to receive a communication to indicate the erase operation for the block did not fail, and wherein a number in a first field of the communication is zero and no useful data is in a second field of the communication.

6. The system of claim 1 , wherein the erase command is to identify the block of the non-volatile memory.

7. The system of claim 1 , wherein the non-volatile memory controller is to document in a table each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

8. A device comprising:

a non-volatile memory to initiate an erase operation for a block of the non-volatile memory in response to an erase command, wherein the block is to include a plurality of sub-blocks; and

a non-volatile memory controller communicatively coupled to the non-volatile memory, the non-volatile memory controller to track a failure of the erase operation for the block on an individual sub-block basis, wherein the non-volatile memory controller is to:

transfer, in response to an indication that the erase operation for the block failed, an erase status enhanced command to the non-volatile memory to obtain an identification made from the erase operation for the block of each individual sub-block in a first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block; and

receive, from the non-volatile memory, a response to the erase status enhanced command including the identification made from the erase operation for the block of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

9. The device of claim 8 , wherein the non-volatile memory controller is to permit use of a second subset of the plurality of sub-blocks that successfully erased during the erase operation for the block.

10. The device of claim 8 , wherein the non-volatile memory controller is to prevent use of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

11. The device of claim 8 , wherein the non-volatile memory controller is to receive a communication to indicate the erase operation for the block did not fail, and wherein a number in a first field of the communication is zero and no useful data is in a second field of the communication.

12. The device of claim 8 , wherein a first field of the response to the erase status enhanced command is one byte of data and a second field of the response to the erase status enhanced command is in a variable number of bytes or a fixed number of bytes.

13. The device of claim 8 , wherein the erase command is to identify the block of the non-volatile memory.

14. The device of claim 8 , wherein the non-volatile memory controller is to document in a table each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

15. A method comprising:

initiating an erase operation for a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks; and

tracking a failure of the erase operation for the block on an individual sub-block basis, wherein tracking the failure includes:

transferring, in response to an indication that the erase operation for the block failed, an erase status enhanced command from a non-volatile memory controller to the non-volatile memory to obtain an identification made from the erase operation for the block of each individual sub-block in a first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block; and

receiving, at the non-volatile memory controller form the non-volatile memory, a response to the erase status enhanced command including the identification made from the erase operation for the block of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

16. The method of claim 15 , further including permitting use of a second subset of the plurality of sub-blocks that successfully erased during the erase operation for the block.

17. The method of claim 15 , further including preventing use of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

18. The method of claim 15 , wherein the non-volatile memory controller is to receive a communication to indicate the erase operation for the block did not fail, and wherein a number in a first field of the communication is zero and no useful data is in a second field of the communication.

19. The method of claim 15 , wherein a first field of the response to the erase status enhanced command is one byte of data and a second field of the response to the erase status enhanced command is a variable number of bytes or a fixed number of bytes.

20. The method of claim 15 , wherein the erase command identifies the block of the non-volatile memory.

21. The method of claim 15 , further including documenting in a table each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

22. The device of claim 8 , wherein the response to the erase status enhanced command includes a first field having a total number of sub-blocks that are in error in the first subset of the plurality of sub-blocks and a second field including the identification made from the erase operation for the block of each individual sub-block in the first subset of the plurality of sub-blocks that failed to erase during the erase operation for the block.

23. The device of claim 8 , wherein the non-volatile memory is to:

receive the erase command;

set all bits in the block to a predetermined value in response to the erase command;

read the bits in the block to determine whether the bits have the predetermined value; and

transfer, in response to a determination that the bits in the block do not have the predetermined value, the indication that the erase operation for the block failed.

24. The device of claim 23 , wherein the predetermined value is a same bit value that is to be set for all the bits in the block.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 063815/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2016
From: RAMALINGAM, ANAND S.; KHAN, JAWAD B.; KALAVADE, PRANAV
To: INTEL CORPORATION
Reel/Frame 040503/0298 →
Continuity (1)
Related Publication 20180088823A1 · Mar 29, 2018