IP Library Granted Patent US 9,866,228
Granted Patent B2
US 9,866,228 · App. 15/280,930 · Granted Jan 9, 2018

Background calibration of interleave timing errors in time-interleaved analog to digital converters

Inventors: Anthony Eugene Zortea (Pipersville, PA); Russell Romano (Allentown, PA)
Assignee: MULTIPHY LTD.
H03M1/1033H03M1/0624H03M1/1215
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Quick Facts
Patent No.
US 9,866,228
App. No.
15/280,930
Granted
Jan 9, 2018
Kind
B2
Abstract

A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), according to which N samples of the input signal are acquired in N different phases and the time-interleave error of each phase is calculated. Then the sign of each of the time-interleave error is extracted and the errors are adjusted by adjusting the timing of erroneous phases. This process is repeated until all the errors are lower than a predefined level.

Claims (16)

1. A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), comprising:

a. acquiring N samples of an input signal in N different phases;

b. calculating the time-interleave error of each phase, wherein the time-interleave error of a phase is the difference between auto-correlations of the input signal evaluated at both sides of the phase;

c. extracting a sign of each said time-interleave error;

d. adjusting the errors of all N difference phases by adjusting the timing of erroneous phases according to said sign; and

e. repeating steps b) to d) above until all said errors are lower than a predefined level.

2. The method of claim 1 , wherein said erroneous phases timing adjustment comprises delaying phases with negative errors that are followed by phases with positive errors.

3. The method of claim 1 , wherein said erroneous phases timing adjustment comprises advancing phases with positive errors that are preceded by phases with negative errors.

4. The method of claim 1 , wherein an average time-interleave error, which exceeds a predefined correction limit, is measured and corrected by adjusting the timing of all of the phases.

5. A method for performing background calibration of interleave timing errors in N order Time-Interleaved Analog to Digital Converters (TIADCs), comprising:

a. acquiring N samples of the input signal in N different phases;

b. calculating the time-interleave error of each phase;

c. extracting a sign of each said time-interleave error;

d. adjusting the errors of all N difference phases by adjusting the timing of erroneous phases according to said sign; and

e. repeating steps b) to d) above until all said errors are lower than a predefined level;

wherein an average time-interleave error, which exceeds a predefined correction limit, is measured and corrected by adjusting the timing of all of the phases.

Assignments (3)
SECURITY INTEREST Recorded Jan 3, 2017
From: MULTIPHY LTD.
To: KREOS CAPITAL IV (EXPERT FUND) LIMITED
Reel/Frame 040818/0449 →
SECURITY INTEREST Recorded Jan 3, 2017
From: MULTIPHY LTD.
To: KREOS CAPITAL V (EXPERT FUND) L.P.
Reel/Frame 040818/0490 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2016
From: ZORTEA, ANTHONY EUGENE; ROMANO, RUSSELL
To: MULTIPHY LTD.
Reel/Frame 039926/0604 →
Continuity (2)
Provisional Application 62234705 · Sep 30, 2015
Related Publication 20170093415A1 · Mar 30, 2017