Frequency-domain ADC flash calibration
A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.
1. A calibration system to calibrate an offset of a comparator of an analog-to-digital (ADC) converter, comprising:
the analog-to-digital converter (ADC), which includes a plurality of comparators that convert an analog input to digital data, the plurality of comparators including the comparator;
a frequency filter to filter out a frequency of the analog input from frequencies of the digital data to produce a filtered signal; and
calibration logic configured to determine a calibration code for the comparator to reduce a power of the digital data and to adjust the offset of the comparator based on the filtered signal.
2. The calibration system of claim 1 , wherein the calibration code for the comparator minimizes the power of the digital data.
3. The calibration system of claim 1 , wherein the comparator converts the analog input to digital data based on the calibration code.
4. The calibration system of claim 1 , further comprising:
a frequency summer that sums the filtered signal to produce a power signal, wherein the calibration logic adjusts the offset of the comparator based on the power signal.
5. The calibration system of claim 1 , wherein the filter is implemented as a time-domain filter or as a fast Fourier transform unit and a frequency-domain filter.
6. The calibration system of claim 1 , wherein the calibration logic is configured to determine a power of the digital data, based on a first calibration code and a second calibration code preceding the first calibration code.
7. The calibration system of claim 1 , wherein the calibration logic is configured to determine a power of digital data, based on each calibration code in a full range of calibration codes of the comparator.
8. A method to calibrate an offset of a comparator of an analog-to-digital (ADC) converter, the method comprising:
converting an analog input to digital data using a plurality of comparators, the plurality of comparators including the comparator;
filtering out a frequency of the analog input from frequencies of the digital data to produce a filtered signal;
determining a calibration code for the comparator to minimize a power of the digital data; and
adjusting the offset of the comparator based on the filtered signal.
9. The method of claim 8 , wherein the calibration code for the comparator minimizes the power of the digital data.
10. The method of claim 8 , further comprising:
converting the analog input to digital data based on the calibration code.
11. The method of claim 8 , further comprising:
summing the filtered signal to produce a power signal; and
adjusting the offset of the comparator based on the power signal.
12. The method of claim 8 , further comprising:
determining that a power of the digital data is less than a predetermined value.
13. The method of claim 8 , further comprising:
determining a power of the digital data, based on a first calibration code and a second calibration code preceding the first calibration code.
14. The method of claim 8 , further comprising:
determining a power of digital data, based on each calibration code in a full range of calibration codes of the comparator.
15. The method of claim 8 , wherein the method is performed as a background calibration procedure.
16. A non-transitory computer-readable medium encoded with instructions that, when executed, cause a processor to perform a method for calibrating an offset of a comparator of an analog-to-digital (ADC) converter, the method comprising:
filtering out a frequency of an analog input from frequencies of digital data received from the ADC to produce a filtered signal;
determining a calibration code for the comparator to minimize a power of the digital data; and
adjusting the offset of the comparator based on the filtered signal, wherein the analog input is converted to the digital data using a plurality of comparators, the plurality of comparators including the comparator.
17. The medium of claim 16 , wherein the calibration code for the comparator minimizes the power of the digital data.
18. The medium of claim 16 , the method further comprising:
converting the analog input to digital data based on the calibration code.
19. The medium of claim 16 , the method further comprising:
summing the filtered signal to produce a power signal; and
adjusting the offset of the comparator based on the power signal.
20. The medium of claim 16 , the method further comprising:
determining that a power of the digital data is less than a predetermined value.
21. The medium of claim 16 , the method further comprising:
determining a power of the digital data, based on a first calibration code and a second calibration code preceding the first calibration code.