Reconfigurable FEC
The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
1. A method for data communication, the method comprising:
receiving data from a plurality of communication lanes, the plurality of communication lanes including a first communication lane and a second communication lane, the first communication lane and the second communication lane operating at n-bit, n being associated with a data width;
determining an operating mode associated with the data;
performing syndrome computation (SC) to generate an equation using a 2n-bit vector if the operating mode is in a 2n-bit mode, the 2n-bit vector including data from the first communication lane and the second communication lane, the 2n-bit vector being stored in a first vector module and a second vector module, the SC computation being performed by a second processing module;
performing syndrome computation (SC) using a second first processing module to generate the equation using a first n-bit vector if the operating mode is in a n-bit mode, the first n-bit vector including data from the first communication lane, the n-bit vector being stored in the first vector module;
solving the equation using a key equation solver (KES) module;
generating a first polynomial and a second polynomial based at least on the equation; and
performing a Chieh Search (CS) using at least the first polynomial to determine an error location.
2. The method of claim 1 further comprising aligning data at least from the first communication lane using an accumulator.
3. The method of claim 1 wherein the operating mode is selected from an n-bit mode, a 2n-bit mode, and a 4n-bit mode.
4. The method of claim 1 further comprising forming the 2n-bit vector using data from the first communication lane and the second communication lane.
5. The method of claim 4 further comprising aligning data from the first communication lane and the second communication lane.
6. The method of claim 1 further comprising storing the data at a buffer.
7. The method of claim 6 further comprising correcting the data stored at the buffer using at least the error location.
8. The method of claim 1 wherein the plurality of communication lanes further comprises a third communication lane and a fourth communication lane operating at n-bit, and
wherein the method further comprising performing syndrome computation (SC) to generate the equation using an 4n-bit vector if the operating mode is in a 4n-bit mode, the 4n-bit vector including data from the first communication lane, the second communication lane, the third communication lane, and the fourth communication lane.
9. The method of claim 1 wherein the first polynomial is associated with the error location and the second polynomial is associated with an error value.
10. The method of claim 9 further comprising determining the error value using Forney algorithm.
11. The method of claim 1 further comprising processing Bose-Chaudhuri-Hocquenghem (BCH) codes associated with the data.
12. The method of claim 1 further comprising processing Reed Solomon codes associated with the data.
13. The method of claim 1 further comprising performing syndrome computation (SC) using a second processing module to generate the equation using a second n-bit vector if the operating mode is in a n-bit mode, a second n-bit vector including data from the second communication lane.
14. The method of claim 1 where n equals to 40.
15. The method of claim 1 further comprising storing the data using one or more accumulators.
16. The method of claim 1 further comprising selecting from two or more root values.
17. A method for data communication, the method comprising:
receiving data from a plurality of communication lanes, the plurality of communication lanes including a first communication lane and a second communication lane, the first communication lane and the second communication lane operating at n-bit, n being associated with a data width;
aligning the data;
selecting an operating mode associated with the data;
performing syndrome computation (SC) to generate an equation using a 2n-bit vector if the operating mode is in a 2n-bit mode, the 2n-bit vector including data from the first communication lane and the second communication lane, the 2n-bit vector being stored in a first vector module and a second vector module, the SC computation being performed by a second processing module;
performing syndrome computation (SC) using a first processing module to generate the equation using a first n-bit vector if the operating mode is in a n-bit mode, the first n-bit vector including data from the first communication lane, the n-bit vector being stored in the first vector module;
solving the equation using a key equation solver (KES) module;
generating a polynomial based at least on the equation; and
performing a Chieh Search (CS) using at least the first polynomial to determine an error location.
18. The method of claim 17 further comprising storing the data using a first-in-first-out (FIFO) buffer.
19. The method of claim 17 wherein the polynomial comprises a syndrome polynomial.
20. A method for data communication, the method comprising:
receiving data from a plurality of communication lanes, the plurality of communication lanes including a first communication lane and a second communication lane, the first communication lane and the second communication lane operating at n-bit, n being associated with a data width;
aligning the data using at least an accumulator;
storing the data at a buffer;
determining an operating mode associated with the data;
performing syndrome computation (SC) to generate an equation using a 2n-bit vector if the operating mode is in a 2n-bit mode, the 2n-bit vector including data from the first communication lane and the second communication lane, the 2n-bit vector being stored in a first vector module and a second vector module, the SC computation being performed by a second processing module;
performing syndrome computation (SC) using a first processing module to generate the equation using a first n-bit vector if the operating mode is in a n-bit mode, the first n-bit vector including data from the first communication lane, the n-bit vector being stored in the first vector module;
solving the equation using a key equation solver (KES) module;
generating a first polynomial and a second polynomial based at least on the equation;
performing a Chieh Search (CS) using at least the first polynomial to determine an error location; and
correcting the data stored at the buffer using at least the error location.