IP Library Granted Patent US 10,216,569
Granted Patent B2
US 10,216,569 · App. 15/284,019 · Granted Feb 26, 2019

Systems and methods for adaptive data storage

Inventors: David Flynn (Sandy, UT); John Strasser (Syracuse, UT); Bill Inskeep (West Valley City, UT)
Assignee: FIO Semiconductor Technologies Limited
G06F11/1044G06F11/1008G06F11/108G06F11/1068G06F12/0253H04L12/4625H04L12/6418H05K7/1444G06F11/1092G06F2211/109G06F2212/2022H04L67/1097
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Quick Facts
Patent No.
US 10,216,569
App. No.
15/284,019
Granted
Feb 26, 2019
Kind
B2
Abstract

A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array.

Claims (59)

1. A method, comprising:

managing, via a storage module, storage operations for a solid-state storage array;

queuing storage requests for the solid-state storage array in an ordered request buffer;

reordering the storage requests in the ordered request buffer, wherein the storage module comprises:

a logical-to-physical translation layer; and

the ordered request buffer, wherein the ordered request buffer is configured to receive storage requests from one or more store clients, and to buffer storage requests received via a bus;

generating, via an error-correcting code write module, an error-correcting code codeword comprising data for storage on the solid-state storage array, wherein the error-correcting code codeword is used to detect errors in data read from the solid-state storage array, correct errors in data read from the solid-state storage array, or a combination thereof;

generating, via a write module, data rows for storage within columns of the solid-state storage array, wherein each of the data rows comprises data of two or more different error-correcting code codewords;

generating, via a parity module, respective parity data for each of the data rows; and

reconstructing, via a data reconstruction module, an uncorrectable error-correcting code codeword of the two or more different error-correcting code codewords by accessing data rows and the respective parity data comprising the two or more different error-correcting code codewords.

2. The method of claim 1 , further comprising:

detecting the uncorrectable error-correcting code codeword in response to a first read operation;

recovering the uncorrectable error-correcting code codeword by reading other error-correcting code codewords within a vertical stripe with the uncorrectable error-correcting code codewords in a second read operation;

decoding the other error-correcting code codewords; and

reconstructing the uncorrectable error-correcting code codewords using the decoded error-correcting code codewords and parity data of the vertical stripe.

3. The method of claim 1 , further comprising performing, via a grooming module, grooming operations.

4. The method of claim 3 , wherein the grooming operations comprise reclaiming storage resources, erasure, wear leveling, refreshing data stored on the solid-state storage array, or some combination thereof.

5. The method of claim 1 , wherein the solid-state storage array comprises flash memory.

6. The method of claim 1 , wherein the solid-state storage array comprises a plurality of physical storage cells configured for persistent data storage.

7. The method of claim 6 , wherein the plurality of physical storage cells is arranged in groups.

8. The method of claim 7 , wherein each group of the groups comprises a page.

9. The method of claim 7 , wherein the groups are partitioned into storage divisions.

10. The method of claim 9 , wherein each storage division of the storage divisions comprises an erase block.

11. The method of claim 1 , wherein the bus comprises a peripheral component interconnect express bus.

12. The method of claim 1 , wherein the logical-to-physical translation layer comprises any-to-any mappings.

13. The method of claim 1 , wherein the storage module is configured to actively scan the solid-state storage array to identify sections of the solid-state storage array to be taken out of service.

14. The method of claim 1 , wherein the data reconstruction module is configured to reconstruct the uncorrectable error-correcting code codeword based on a horizontal stripe configuration, a vertical stripe configuration, the parity, or some combination thereof.

15. The method of claim 1 , further comprising combining, via an adaptive schedule module, two or more read operations into a combined read operation, wherein the two or more read operations correspond to error-correcting code codewords stored within different sets of storage elements of the solid-state storage array.

16. An apparatus, comprising:

a bus;

a storage module configured to:

manage storage operations for a solid-state storage array;

queue storage requests for the solid-state storage array in an ordered request buffer; and

reorder the storage requests in the ordered request buffer, wherein the storage module comprises:

a logical-to-physical translation layer; and

the ordered request buffer, wherein the ordered request buffer is configured to receive storage requests from one or more store clients, and to buffer storage requests received via the bus;

an error-correcting code write module configured to generate an error-correcting code codeword comprising data for storage on the solid-state storage array, wherein the error-correcting code codeword is used to detect errors in data read from the solid-state storage array, correct errors in data read from the solid-state storage array, or a combination thereof;

a write module configured to generate data rows for storage within columns of the solid-state storage array, wherein each of the data rows comprises data of two or more different error-correcting code codewords;

a parity module configured to generate respective parity data for each of the data rows; and

a data reconstruction module configured to reconstruct an uncorrectable error-correcting code codeword of the two or more different error-correcting code codewords by accessing data rows and the respective parity data comprising the two or more different error-correcting code codewords.

17. The apparatus of claim 16 , further comprising:

an error-correcting code read module configured to detect the uncorrectable error-correcting code codeword in response to a first read operation; and

a data recovery module configured to:

recover the uncorrectable error-correcting code codeword by reading other error-correcting code codewords within a vertical stripe with the uncorrectable error-correcting code codewords in a second read operation;

decode the other error-correcting code codewords; and

reconstruct the uncorrectable error-correcting code codewords using the decoded error-correcting code codewords and parity data of the vertical stripe.

18. The apparatus of claim 16 , further comprising a groomer module configured to perform grooming operations.

19. The apparatus of claim 18 , wherein the grooming operations comprise reclaiming storage resources, erasure, wear leveling, refreshing data stored on the solid-state storage array, or some combination thereof.

20. The apparatus of claim 16 , wherein the solid-state storage array comprises flash memory.

21. The apparatus of claim 16 , wherein the solid-state storage array comprises a plurality of physical storage cells configured for persistent data storage.

22. The apparatus of claim 21 , wherein the plurality of physical storage cells is arranged in groups.

23. The apparatus of claim 22 , wherein each group of the groups comprises a page.

24. The apparatus of claim 22 , wherein the groups are partitioned into storage divisions.

25. The apparatus of claim 24 , wherein each storage division of the storage divisions comprises an erase block.

26. The apparatus of claim 16 , wherein the bus comprises a peripheral component interconnect express bus.

27. The apparatus of claim 16 , wherein the logical-to-physical translation layer comprises any-to-any mappings.

28. The apparatus of claim 16 , wherein the storage module is configured to actively scan the solid-state storage array to identify sections of the solid-state storage array to be taken out of service.

29. The apparatus of claim 16 , wherein the data reconstruction module is configured to reconstruct the uncorrectable error-correcting code codeword based on a horizontal stripe configuration, a vertical stripe configuration, the parity, or some combination thereof.

30. The apparatus of claim 16 , further comprising an adaptive schedule module configured to combine two or more read operations into a combined read operation, wherein the two or more read operations correspond to error-correcting code codewords stored within different sets of storage elements of the solid-state storage array.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 052853 FRAME: 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 15, 2021
From: UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 058223/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 15, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
To: UNIFICATION TECHNOLOGIES LLC
Reel/Frame 058134/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2020
From: ACACIA RESEARCH GROUP LLC
To: UNIFICATION TECHNOLOGIES LLC
Reel/Frame 052096/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2020
From: FIO SEMICONDUCTOR TECHNOLOGIES, LLC
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 052095/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2019
From: LONGITUDE ENTERPRISE FLASH S.A.R.I.
To: FIO SEMICONDUCTOR TECHNOLOGIES, LLC
Reel/Frame 048931/0864 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT DOCUMENT FILED PREVIOUSLY RECORDED ON REEL 047702 FRAME 0413. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 16, 2019
From: LONGITUDE ENTERPRISE FLASH S.A.R.I.
To: FIO SEMICONDUCTOR TECHNOLOGIES, LLC
Reel/Frame 048918/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2018
From: LONGITUDE ENTERPRISE FLASH S.A.R.I.
To: FIO SEMICONDUCTOR TECHNOLOGIES LIMITED
Reel/Frame 047702/0413 →
Continuity (8)
Continuation 13784705 · Mar 4, 2013
Continuation In Part 13296834 · Nov 15, 2011
Continuation In Part 11952101 · Dec 6, 2007
Provisional Application 61606253 · Mar 2, 2012
Provisional Application 61606755 · Mar 5, 2012
Provisional Application 60873111 · Dec 6, 2006
Provisional Application 60974470 · Sep 22, 2007
Related Publication 20170017542A1 · Jan 19, 2017