IP Library Granted Patent US 10,361,224
Granted Patent B2
US 10,361,224 · App. 15/284,881 · Granted Jul 23, 2019

Display device

Inventor: Yuuichi Takenaka (Hyogo, JP)
Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
H01L27/124G02F1/13452G02F1/136286H01L24/16H01L24/29H01L24/30H01L24/73H01L24/83H01L27/1244H01L27/3276H01L2224/16147H01L2224/29099H01L2224/73203H01L2224/83224H01L2224/83851
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Quick Facts
Patent No.
US 10,361,224
App. No.
15/284,881
Granted
Jul 23, 2019
Kind
B2
Abstract

A display device comprises: a display panel; a metallic wiring formed in the display panel; and a semiconductor integrated circuit element connected to the display panel through a UV curing anisotropy conductive film, wherein the semiconductor integrated circuit element includes a plurality of bumps, the metallic wiring is electrically connected to the bumps through the UV curing anisotropy conductive film, the metallic wiring includes a plurality of openings, and at least one of the bumps is disposed between two adjacent openings closest to each other in the plurality of openings.

Claims (39)

1. A display device comprising:

a display panel;

a metallic wiring formed in the display panel; and

a semiconductor integrated circuit element connected to the display panel through a UV curing anisotropy conductive film,

wherein the semiconductor integrated circuit element includes a plurality of bumps,

the metallic wiring is electrically connected to the bumps through the UV curing anisotropy conductive film,

the metallic wiring includes a plurality of openings,

at least one of the bumps is disposed between two adjacent openings closest to each other in the plurality of openings,

each of the bumps does not overlap with any opening among the plurality of openings in a plan view,

the display device further comprises a metallic layer disposed further away from the semiconductor integrated circuit than the metallic wiring,

the plurality of openings included in the metallic wiring is a first plurality of openings,

the metallic layer includes a second plurality of openings,

at least one of the openings of the first plurality of openings overlaps a corresponding one of the openings of the second plurality of openings, and

an area of the at least one of the openings of the first plurality of openings is larger than an area of the corresponding one of the openings of the second plurality of openings.

2. The display device according to claim 1 , wherein the plurality of openings are formed into a lattice shape at an interval longer than a length in a longitudinal direction of the bump.

3. The display device according to claim 1 , wherein the plurality of openings are arranged in a zigzag manner.

4. The display device according to claim 1 , wherein each of the plurality of openings is formed into a square or circular shape.

5. The display device according to claim 1 , wherein at least one of the openings is located in a region overlapping the semiconductor integrated circuit element in a plan view, and

at least one of the openings is located outside the region overlapping the semiconductor integrated circuit element in a plan view.

6. The display device according to claim 1 , wherein the metallic wiring includes:

a narrow wiring part having a width narrower than a UV excitable distance of the UV curing anisotropy conductive film; and

a wide wiring part having a width wider than the UV excitable distance of the UV curing anisotropy conductive film,

wherein the plurality of openings are not formed in the narrow wiring part, and

the plurality of openings are formed in the wide wiring part.

7. The display device according to claim 1 , wherein the at least one of the bumps is disposed between the two adjacent openings in a cross-sectional view taken along a longitudinal direction of the at least one of the bumps.

8. A display device comprising:

a display panel;

a metallic wiring formed in the display panel; and

a semiconductor integrated circuit element connected to the display panel through a UV curing anisotropy conductive film,

wherein the semiconductor integrated circuit element includes a plurality of bumps,

the metallic wiring is electrically connected to the bumps through the UV curing anisotropy conductive film,

the metallic wiring includes a plurality of openings,

at least one of the bumps is disposed between two adjacent openings closest to each other in the plurality of openings,

each of the bumps does not overlap with any opening among the plurality of openings in a plan view,

the metallic wiring includes:

a narrow wiring part having a width narrower than a UV excitable distance of the UV curing anisotropy conductive film; and

a wide wiring part having a width wider than the UV excitable distance of the UV curing anisotropy conductive film,

the plurality of openings are not formed in the narrow wiring part, and

the plurality of openings are formed in the wide wiring part.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2023
From: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 064292/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2017
From: TAKENAKA, YUUICHI
To: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
Reel/Frame 041851/0517 →
Priority Claims (1)
JP 2015-201546 · Oct 9, 2015 · national
Continuity (1)
Related Publication 20170104008A1 · Apr 13, 2017