On-chip test pattern generation

1. A chip, comprising:

an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and

an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains,

wherein the on-chip signal generator is configured to provide the test pattern signal having a codeword length N, and

wherein plurality of logic elements is configured to form M scan chains,

wherein N is smaller than M, and

wherein the chip further comprises a decompressor configured to translate the test pattern signal having the codeword length of N into a decompressed test pattern signal having a codeword length of M, or

wherein the on-chip signal generator is configured to provide the test pattern signal having a codeword length of N,

wherein the plurality of logic elements is configured to form M scan chains, and

wherein N equals M.

2. The chip of claim 1 ,

wherein the on-chip signal generator comprises a linear feedback shift register.

3. The chip of claim 1 , wherein the on-chip signal generator comprises less than 100,000 transistors.

4. The chip of claim 1 , further comprising:

an external test mode pin connected with the on-chip signal generator and the integrated circuit,

wherein the on-chip signal generator is configured to initialize in response to receiving a setup signal via the external test mode pin, and

wherein the plurality of logic elements is configured to form the scan chains in response to receiving the setup signal via the external test mode pin.

5. The chip of claim 4 , further comprising:

an external clock pin connected with the on-chip signal generator and selectively connected with the integrated circuit,

wherein the on-chip signal generator is configured to provide different states of the test pattern signal depending on a clock signal received via the external clock pin,

wherein each one of the plurality of logic elements is configured to toggle through different states depending on the clock signal and the test pattern signal, and

wherein an IEEE Test Access Port comprises the external clock pin and the external test mode pin.

6. The chip of claim 1 ,

wherein the test mode is a burn-in exercise of the plurality of flip-flops.

7. A chip, comprising:

an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and

an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains;

an external clock pin connected with the signal generator and selectively connected with the integrated circuit,

wherein the on-chip signal generator is configured to provide different states of the test pattern signal depending on a clock signal received via the external clock pin, and

wherein each one of the plurality of logic elements is configured to toggle through different states depending on the clock signal and the test pattern signal.

8. The chip of claim 7 , further comprising:

at least one switch configured to connect, in the test mode, the external clock pin with the integrated circuit and configured to disconnect, in a further mode different to the test mode, the external clock pin from the integrated circuit.

9. A chip, comprising:

an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and

an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains;

a plurality of external scan control pins selectively connected with the integrated circuit, and

at least one switch configured to disconnect, in the test mode, the plurality of external scan control pins from the plurality of scan chains,

wherein the at least one switch is configured to connect, in a further mode other than the test mode, the plurality of external scan control pins to the plurality of scan chains.

10. The chip of claim 9 ,

wherein the plurality of external scan control pins is further configured to provide a further clock signal to the plurality of scan chains, and

wherein each one of the plurality of logic elements is configured to toggle through different states depending on the further clock signal and the further test pattern signal.