Compound semiconductor based inverter

1. A compound semiconductor inverter circuit, comprising:

a pull-down FET, integrated with a compound semiconductor substrate;

a depletion mode pull-up FET, integrated with the compound semiconductor substrate;

a bias current source, integrated with the compound semiconductor substrate, the bias current source electrically connected to a source terminal of the depletion mode pull-up FET to keep the depletion mode pull-up FET on by providing a bias current when the pull-down FET is off; and

a voltage drop circuit, electrically coupled between the source terminal of the depletion mode pull-up FET and a gate terminal of the depletion mode pull-up FET, and electrically coupled to a drain terminal of the pull-down FET to maintain a source-gate bias voltage between the source and gate terminals of the depletion mode pull-up FET to keep the depletion mode pull-up FET on at least when the pull-down FET is turned on and sinking current through the voltage drop circuit.

2. The compound semiconductor inverter circuit of claim 1 , wherein the pull-down FET is an enhancement mode pull-down FET.

3. The compound semiconductor inverter circuit of claim 1 , wherein the pull-down FET is a depletion mode pull-down FET.

4. The compound semiconductor inverter circuit of claim 1 , wherein the voltage drop circuit comprises:

a diode integrated with the compound semiconductor substrate.

5. The compound semiconductor inverter circuit of claim 1 , wherein the voltage drop circuit comprises:

a resistor integrated with the compound semiconductor substrate.

6. The compound semiconductor inverter circuit of claim 1 , wherein the compound semiconductor substrate is a III-V compound based semiconductor substrate.

7. The compound semiconductor inverter circuit of claim 1 , wherein

the compound semiconductor inverter circuit has an input node coupled to a gate terminal of the pull-down FET, and an output node coupled to the source terminal of the depletion mode pull-up FET,

wherein responsive to the input node receiving a logic low input voltage, the output node provides a logic high output voltage equal to an upper supply voltage applied to the inverter circuit with the bias current circuit providing a bias current to keep the depletion mode pull-up FET on while the pull-down FET is off, and

wherein responsive to the input node receiving a logic high input voltage, the output node provides a logic low output voltage equal to a magnitude of a turn-on threshold voltage of the depletion mode pull-up FET.

8. The compound semiconductor inverter circuit of claim 1 ,

wherein the compound semiconductor inverter circuit has an input node coupled to a gate terminal of the pull-down FET, and an output node coupled to the source terminal of the depletion mode pull-down FET,

wherein responsive to the input node receiving an input change between a logic low input voltage and a logic high input voltage, the output node provides an output change between a high output voltage and a logic low output voltage with a settling time between about 50 ns and 80 ns.

9. The compound semiconductor inverter circuit of claim 1 , wherein

at least one of the pull-down FET and the depletion mode pull-up FET has an on-mode current of about 5 microamperes.

10. A device, comprising:

a circuit package with a plurality of attenuation input leads;

a digital attenuator in the circuit package that receives an input signal and outputs an output signal that is an attenuated version of the input signal with an attenuation determined by a plurality of attenuation control signal inputs received by the digital attenuator;

a plurality of compound semiconductor inverter circuits in the circuit package and integrated with a compound semiconductor substrate, each compound semiconductor inverter circuit of the plurality of compound semiconductor inverter circuits including:

a pull-down FET, integrated with the compound semiconductor substrate;

a depletion mode pull-up FET, integrated with the compound semiconductor substrate;

a bias current source, integrated with the compound semiconductor substrate, the bias current source electrically connected to a source terminal of the depletion mode pull-up FET to keep the depletion mode pull-up FET on; and

a voltage drop circuit, electrically coupled between the source terminal of the depletion mode pull-up FET and a gate terminal of the depletion mode pull-up FET, and electrically coupled to a drain terminal of the pull-down FET to maintain a source-gate bias voltage between the source and gate terminals of the depletion mode FET to keep the depletion mode pull-up FET on at least when the pull-down FET is turned on and sinking current through the voltage drop circuit,

wherein the plurality of compound semiconductor inverter circuits have inverter input nodes electrically coupled to the plurality of attenuation input leads, and the plurality of compound semiconductor inverter circuits have inverter output nodes electrically coupled to the plurality of attenuation control signal inputs.

11. The device of claim 10 , wherein the pull-down FET of at least one of the plurality of compound semiconductor inverter circuits is an enhancement mode pull-down FET.

12. The device of claim 10 , wherein the pull-down FET of at least one of the plurality of compound semiconductor inverter circuits is a depletion mode pull-down FET.

13. The device of claim 10 , wherein the voltage drop circuit of at least one of the plurality of compound semiconductor inverter circuits comprises:

a diode integrated with the compound semiconductor substrate.

14. The device of claim 10 , wherein the voltage drop circuit of at least one of the plurality of compound semiconductor inverter circuits comprises:

a resistor integrated with the compound semiconductor substrate.

15. The device of claim 10 , wherein the compound semiconductor substrate is a III-V compound based semiconductor substrate.

16. The device of claim 10 ,

wherein at least one of the plurality of compound semiconductor inverter circuits has an input node coupled to a gate terminal of the pull-down FET, and an output node coupled to the source terminal of the depletion mode pull-up FET,

wherein responsive to the input node receiving a logic low input voltage, the output node provides a logic high output voltage equal to an upper supply voltage applied to the inverter circuit, and

wherein responsive to the input node receiving a logic high input voltage, the output node provides a logic low output voltage equal to a magnitude of a turn-on threshold voltage of the pull-up FET.

17. The device of claim 10 ,

wherein at least one of the plurality of compound semiconductor inverter circuits has an input node coupled to a gate terminal of the pull-down FET, and an output node coupled to the source terminal of the depletion mode pull-up FET,

wherein responsive to the input node receiving an input change between a logic low input voltage and a logic high input voltage, the output node provides an output change between a high output voltage and a logic low output voltage with a settling time between about 50 ns and 80 ns.

18. The device of claim 10 ,

wherein for at least one of the plurality of compound semiconductor inverter circuits, the pull-down FET and the depletion mode pull-up FET has an on-mode current of about 5 microamperes.

19. A method of inverting an input signal using a compound semiconductor inverter circuit including a depletion mode pull-up FET and a pull-down FET, the method comprising:

responsive to an inverter input node receiving a logic high input voltage, turning on a pull-down FET and providing a logic low output voltage equal to a magnitude of a turn-on threshold voltage of the depletion mode pull-up FET while biasing the depletion mode pull-up FET on via a pull-up FET bias current and a pull-up FET gate-source bias circuit; and

responsive to the inverter input node receiving a logic low input voltage, turning off the pull-down FET and providing a logic high output voltage equal to an upper supply voltage applied to the inverter circuit while continuing to provide the pull-up FET bias current when the pull-down FET is off.

20. The method of claim 19 ,

wherein the compound semiconductor inverter circuit has an input node coupled to a gate terminal of the pull-down FET, and an output node coupled to the source terminal of the depletion mode pull-up FET,

wherein responsive to the input node receiving an input change between the logic low input voltage and the logic high input voltage, the output node provides an output change between the high output voltage and the logic low output voltage with a settling time between about 50 ns and 80 ns.