Method of forming a semiconductor device termination and structure therefor
At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
1. An edge termination structure of a semiconductor device comprising:
a substrate of a first conductivity type;
a first layer of the first conductivity type overlying the substrate where a trench is formed in the first layer, the first layer having a first surface that faces away from the substrate;
the semiconductor device including an active region and an edge termination area wherein the edge termination area is external to the active region with the edge termination structure within the edge termination area and the edge termination structure separated from the active region by a portion of the first layer, the edge termination structure including:
a second layer having a first portion that is adjacent to and substantially parallel to sidewalls of the trench, and having a second portion overlying a bottomsurface of the trench;
a separator layer formed overlying the second layer where the separator layer is at least one of an intrinsic layer or a dielectric layer;
a third layer overlying the separator layer, wherein a conductivity type of the third layer is different than a conductivity type of the second layer, the third layer having a first surface in a plane substantially parallel to the first surface of the first layer;
a buffer region overlying the third layer wherein the buffer region has a sidewall that extends into the trench and wherein the third layer is adjacent an entire length of the sidewall of the buffer region; and
a dielectric layer on and in direct contact with the first surface of the third layer.
2. The semiconductor device according to claim 1 , further comprising a second buffer layer underlying the first layer where a portion of the edge termination structure is adjacent to the second buffer layer and where the second buffer layer overlies the semiconductor substrate.
3. The edge termination structure according to claim 1 , where the buffer region comprises:
an insulating layer overlying the third layer, and a void at least partially bounded by the insulating layer wherein the void includes a gas.
4. The edge termination structure of claim 1 further including the buffer region overlying a first portion of the third layer, wherein a conductivity type of the first portion is the same as the conductivity type of the third layer.
5. The semiconductor device according to claim 4 , where the third layer and the first portion of the third layer are formed from a first common layer.
6. The edge termination structure of claim 4 wherein the first portion of the third layer is overlying the second portion of the second layer, wherein a conductivity type of the first portion of the second layer is the same as the conductivity type of the second layer.
7. The semiconductor device according to claim 6 , where the second layer and the second portion of the second layer are formed from a second common layer.
8. The edge termination structure of claim 4 wherein the dielectric layer extends to be on and in direct contact with the buffer region.
9. The edge termination structure of claim 1 wherein the dielectric layer extends to be on and in direct contact with the second layer.
10. The edge termination structure of claim 1 wherein the buffer region has a length that extends in a first direction away from a surface of the first layer toward the substrate and having a width along the length wherein the buffer region does not extend laterally in a second direction for a second distance that is greater than the width.
11. The edge termination structure of claim 1 wherein the separator layer extends adjacent to an entire length of a sidewall of the third layer.
12. The edge termination structure of claim 1 wherein the third layer extends along an entire length of a sidewall of the separator layer.