Real time memory address translation device

1. A system, comprising:

a dynamic random access memory (DRAM) translation unit (DTU) configured to map a bus address in a bus address super page to a device address in a device address super page, the DTU comprising:

a device state array comprising N d entries, each of which is a device address super page, and N d is an equivalent number of super pages covering a device address range that corresponds to an installed DRAM capacity; and

a bus map comprising N b entries, each of which is a bus address super page, and N b is an equivalent number of super pages covering a bus address range, N b being equal to or larger than N d ,

wherein the DTU is configured to map the bus address super page to the device address super page within a predetermined period of time to meet real-time requirements of DRAM requests having an upper-bound response time.

2. The system of claim 1 , further comprising an integrated circuit chip that includes the device state array and the bus map.

3. The system of claim 1 , wherein the DTU further comprises a scrub background agent configured to monitor the N d entries to determine if one or more device address super pages need scrubbing.

4. The system of claim 3 , wherein the DTU further comprises a scrubber configured to scrub the one or more device address super pages determined to need scrubbing and to change a state of the scrubbed one or more device address super pages to active.

5. The system of claim 4 , wherein the scrubber is configured to scrub the one or more device address super pages determined to need scrubbing by issuing a device write command with a zero value.

6. The system of claim 1 , wherein the DTU further comprises an allocator configured to identify unmapped device address super pages that are available for mapping.

7. The system of claim 6 , wherein the allocator is implemented in software and is further configured to map one or more bus address super pages to one or more device address super pages, and to unmap one or more bus address super pages from one or more device address super pages.

8. The system of claim 6 , wherein the allocator is implemented in hardware.

9. The system of claim 6 , wherein the allocator is further configured to enforce mappings between bus address super pages and device address super pages, and the allocator is implemented in hardware.

10. The system of claim 1 , further comprising at least one memory controller.

11. The system of claim 1 , wherein the device state array and the bus map are updated contemporaneously.

12. A method, comprising:

(a) receiving a request from a requestor at a dynamic random access memory (DRAM) translation unit (DTU) regarding addressing needs of the requestor, the addressing needs comprising a first bus address to be mapped and a first bus address super page that contains the first bus address;

(b) polling for a free count that indicates a number of device address super pages having an inactive state that is available for mapping;

(c) in response to determining that the free count is greater than zero, mapping the first bus address super page to a first device address super page by writing a value to the first bus address super page and reading the first bus address to verify that a valid flag has been set; and

(d) if no valid flag is set, repeating steps (b) and (c).

13. The method of claim 12 , further comprising:

(e) identifying a second bus address to unmap and a second bus address super page that contains the second bus address;

(f) writing a value to the second bus address super page and reading the second bus address to verify that a valid flag is not set; and

(g) outputting an error message if the valid flag is set.

14. The method of claim 12 , wherein the mapping of the first bus address super page to the first device address super page is performed within a fixed period of time to meet real-time requirements of DRAM requests having an upper-bound response time.

15. The method of claim 12 , wherein the mapping of the first bus address super page to the first device address super page is performed using an on-chip device state array and a bus map.

16. The method of claim 15 , further comprising:

monitoring entries in the device state array to determine if one or more device address super pages need scrubbing; and

generating work items based upon the one or more device address super pages determined to need scrubbing.

17. The method of claim 16 , further comprising:

receiving the generated work items; and

scrubbing the one or more device address super pages by issuing a device write command with a zero value.

18. A dynamic random access memory (DRAM) translation unit (DTU) for mapping a bus address to a device address, comprising:

a device state array comprising a plurality of device page entries, each of which corresponds to a device page, the plurality of device page entries covering a device address range that corresponds to an installed DRAM capacity;

a bus map comprising a plurality of bus page entries, each of which corresponds to a bus page;

an allocator configured to manage availability of the device pages, wherein the allocator is further configured to map a first bus address super page to first device address super page by writing a value to the first bus address super page and, reading a first bus address in the first bus address super page to verify that a valid flag has been set;

a scrub background agent configured to monitor the plurality of device page entries to determine if one or more device pages need scrubbing; and

a scrubber configured to scrub the one or more device pages determined to need scrubbing by issuing a device write command with a zero value.

19. The DTU of claim 18 , wherein the number of bus page entries is equal to or greater than the number of device page entries.

20. The DTU of claim 18 , wherein the device write command is configured to fill the one or more device pages determined to need scrubbing with zeros.