PROCESSING BYPASS DIRECTORY TRACKING SYSTEM AND METHOD
A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which state of a bypass path processing information is at.
1 . A method comprising:
accessing information in a directory for a data processing pipeline, wherein the information comprises a sequence of hits;
determining a configuration of values of the bits; and
identifying a location of data in the data processing pipeline based on the configuration.
2 . The method of claim 1 , wherein the data processing pipeline comprises a bypass register file including a plurality of storage elements, and wherein the configuration of the values of the bits identifies a storage element of the plurality of storage elements that is the location of the data.
3 . The method of claim 1 , wherein the data processing pipeline comprises an architectural register file that is identified as the location of the data when all bits in the sequence of bits have a same value.
4 . The method of claim 1 , wherein said determining comprises:
examining the values of the bits to identify a transition point at which a first bit in the sequence of bits that has a first value is adjacent to a second bit in the sequence of bits that has a second value different from the first value; and
identifying a location of the data in the data processing pipeline based on the transition point.
5 . The method of claim 4 , wherein the data processing pipeline comprises a bypass register file including a plurality of storage elements, wherein each bit in the sequence of bits is associated with a respective storage element of the plurality of storage elements, and wherein the location of the data is a storage element in the bypass register file associated with the second bit.
6 . The method of claim 1 , further comprising setting the values of the bits with a head pointer.
7 . The method of claim 1 , wherein said identifying comprises:
combining logically values of pairs of bits in the sequence of bits to produce select signals; and
using the select signals to identify the location of the data.
8 . A system comprising:
a processing component coupled to a data processing pipeline;
memory coupled to the data processing pipeline and comprising a directory for the data processing pipeline; and
decode logic coupled to the memory, wherein the decode logic is configured to access information in the directory, wherein, the information comprises a sequence of bits having binary values, wherein the decode logic is further configured to determine a configuration of the values of the bits, and wherein a location, of data in the data processing pipeline is identified based on the configuration.
9 . The system of claim 8 , wherein the data processing pipeline comprises a bypass register file including a plurality of storage elements, and wherein the configuration of the values of the bits identifies a storage element of the plurality of storage elements that is the location of the data.
10 . The system of claim 8 , wherein the data processing pipeline
comprises an architectural register file that is identified as the location of the data when all bits in the sequence of bits have a same binary value.
11 . The system of claim 8 , wherein the decode logic Is further configured to examine the values of the bits to identity a transition point at which a first bit in the sequence of bits that has a first binary value is adjacent to a second bit in the sequence of bits that has a second binary value different from the first binary value, and wherein the location of the data in the data processing pipeline is identified based on the transition point.
12 . The system of claim 11 , wherein the data processing pipeline comprises a bypass register file including a plurality of storage elements, wherein each bit in the sequence of bits is associated with a respective storage element of the plurality of storage elements, and wherein the location of the data is a storage element in the bypass register file associated with the second bit.
13 . The system of claim 8 , further configured to set the values of the bits.
14 . The system of claim 8 , wherein the decode logic is further configured to combine logically values of pairs of bits in the sequence of bits to produce select signals and to use the select signals to identify the location of the data.
15 . A system comprising:
means for accessing information in a directory for a data processing pipeline, wherein, the information, comprises a sequence of bits;
means for determining a configuration of values of the bits; and
means for identifying a location of data in the data processing pipeline based on the configuration.
16 . The system of claim 15 , wherein the data processing pipeline comprises a bypass register file including a plurality of storage elements, and wherein the configuration of the values of the bits identifies a storage element of the plurality of storage elements that is the location of the data.
17 . The system of claim 15 , wherein the data processing pipeline comprises an architectural register file that is identified as the location of the data when all bits in the sequence of bits have a same value.
18 . The system of claim 15 , wherein the means for determining comprises:
means for examining the values of the bits to identify a transition point at which a first bit in the sequence of bits that has a first value is adjacent to a second bit in the sequence of bits that has a second value different from the first value; and
means for Identifying a location of the data in the data processing pipeline based on the transition point.
19 . The system of claim 18 , wherein the data processing pipeline comprises a bypass register file including a plurality of storage elements, wherein each bit in the sequence of bits is associated with a respective storage element of the plurality of storage elements, and wherein the location of the data is a storage element in the register file associated with the second bit.
20 . The system of claim 15 , wherein the means for identifying comprises:
means for combining logically values of pairs of bits in the sequence of bits to produce select signals; and
means for using the select signals to identify the location of the data.