Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
View Patent ↗A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
1. A non-volatile semiconductor memory device comprising:
a memory cell capable of reading a status of multi-bit data to be written when a plurality of read voltages are applied to a control gate of the memory cell, among the plurality of read voltages include a first read voltage, a second read voltage, and a third read voltage increasing in this order; and
a control circuit configured to control a voltage applied to the control gate of the memory cell,
wherein the control circuit performs a first read operation and a second read operation between two program operations of applying a write voltage used to write multi-bit data to the memory cell to the control gate of the memory cell in continuous cycles, and
wherein the control circuit performs the first read operation while a voltage between the first read voltage and the second read voltage is applied to the control gate of the memory cell and the second read operation while a voltage between the first read voltage and the second read voltage is applied to the control gate of the memory cell.
2. The device according to claim 1 , wherein the control circuit performs the first read operation while the voltage between the first read voltage and the second read voltage is applied to the control gate of the memory cell and then performs the second read operation while the voltage between the first read voltage and the second read voltage is applied to the control gate of the memory cell.
3. The device according to claim 2 , wherein the voltage of the first read operation is at a level closer to the first read voltage than the second read voltage and the voltage of the second read operation is at a level closer to the first read voltage than the second read voltage.
4. The device according to claim 2 , wherein a level of the voltage applied in the first read operation is closer to the first read voltage than a level of the voltage applied in the second read operation.
5. The device according to claim 1 , wherein the control circuit performs the first read operation while the voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell and then performs the second read operation while the voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell.
6. The device according to claim 1 , wherein the control circuit further performs another first read operation while a voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell and another second read operation while a voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell.
7. A non-volatile semiconductor memory device comprising:
a memory cell capable of reading a status of multi-bit data to be written when a plurality of read voltages are applied to a control gate of the memory cell, among the plurality of read voltages include a first read voltage, a second read voltage, and a third read voltage increasing in this order; and
a control circuit configured to control a voltage applied to the control gate of the memory cell,
wherein the control circuit performs a first read operation and a second read operation between two program operations of applying a write voltage used to write multi-bit data to the memory cell to the control gate of the memory cell in continuous cycles, and
wherein the control circuit performs the first read operation while a voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell and the second read operation while a voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell.
8. The device according to claim 7 , wherein the control circuit performs the first read operation while the voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell and then performs the second read operation while the voltage between the second read voltage and the third read voltage is applied to the control gate of the memory cell.
9. The device according to claim 8 , wherein the voltage of the first read operation is at a level closer to the second read voltage than the third read voltage and the voltage of the second read operation is at a level closer to the second read voltage than the third read voltage.
10. The device according to claim 8 , wherein a level of the voltage applied in the first read operation is closer to the second read voltage than a level of the voltage applied in the second read operation.
11. The device according to claim 7 , wherein the first read voltage is lowest read voltage among the plurality of read voltages, the second read voltage is second lowest read voltage among the plurality of read voltages, and the third read voltage is third lowest read voltage among the plurality of read voltages.
12. A non-volatile semiconductor memory device comprising:
a memory cell array including a plurality of memory cells capable of having a plurality of threshold voltage distributions including at least a first threshold voltage distribution, a second threshold voltage distribution, and a third threshold voltage distribution formed therein, and a word line connected to a control gate of each of the memory cells, among the plurality of threshold voltage distributions, the first threshold voltage distribution having the lowest threshold value, the second threshold voltage distribution having the second lowest threshold value, and the third threshold voltage distribution having the third lowest threshold value; and
a control circuit configured to apply at least a first voltage and a second voltage to the word line when reading data stored in the memory cell by checking a threshold voltage of the memory cell, the first voltage being used to determine whether the threshold voltage of the memory cell is in a range within or over the second threshold voltage distribution or not, the second voltage being used to determine whether the threshold voltage of the memory cell is in a range within or over the third threshold voltage distribution or not,
wherein the control circuit is, when writing data to the memory cell, configured to perform a program operation of applying a write voltage to the word line and, if data writing is not completed in the program operation, perform another program operation of applying the write voltage increased by a step-up voltage to the word line, and wherein writing data to the memory cell includes performing two read operations between an n-th program operation and an (n+1)-th program operation (where n is an integer of 1 or greater) while a voltage equal to or greater than the first voltage and smaller than the second voltage is applied to the word line.
13. The device according to claim 12 , wherein the voltage of the read operations is at a level closer to the first voltage than the second voltage.