IP Library Granted Patent US 9,824,942
Granted Patent B2
US 9,824,942 · App. 15/304,060 · Granted Nov 21, 2017

Method of manufacturing thin-film transistor substrate including a copper alloy film

Inventor: Tohru Saitoh (Tokyo, JP)
Assignee: JOLED INC.
H01L22/20G09F9/30H01L21/02068H01L21/28H01L21/441H01L29/45H01L29/66969H01L29/786H01L29/7869H01L51/50
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Quick Facts
Patent No.
US 9,824,942
App. No.
15/304,060
Granted
Nov 21, 2017
Kind
B2
Abstract

A method of manufacturing a thin-film transistor (TFT) substrate including a thin-film transistor having a CuMn alloy film. The method includes controlling a contact resistance of a surface of the CuMn alloy film on the basis of a contact angle of the surface of the CuMn alloy film.

Claims (46)

1. A method of manufacturing a thin-film transistor substrate including a thin-film transistor having a CuMn alloy film, the method comprising:

forming the CuMn alloy film; and

controlling a contact resistance of a surface of the CuMn alloy film on a basis of a contact angle of the surface of the CuMn alloy film, wherein

in the controlling, the contact resistance of the surface of the CuMn alloy film is controlled on a basis of a pre-calculated correlation between the contact angle of the surface of the CuMn alloy film and the contact resistance of the surface of the CuMn alloy film.

2. The method of manufacturing the thin-film transistor substrate according to claim 1 , further comprising:

depositing an insulating layer on the CuMn alloy film;

exposing the CuMn alloy film by forming a contact hole through the insulating layer; and

forming an ITO film on the CuMn alloy film via the contact hole, wherein

the controlling is performed between the exposing and the forming of the ITO film.

3. The method of manufacturing the thin-film transistor substrate according to claim 1 , wherein the contact angle is between 40 and 65 degrees.

4. The method of manufacturing the thin-film transistor substrate according to claim 1 , wherein the contact angle is a contact angle with respect to water.

5. The method of manufacturing the thin-film transistor substrate according to claim 1 , further comprising:

depositing an insulating layer on the CuMn alloy film; and

exposing the CuMn surface for a predetermined period of time,

wherein the predetermined period of time is a time period starting from removing a resist film when forming a contact hole through the insulating layer.

6. The method of manufacturing the thin-film transistor substrate according to claim 1 , wherein the contact angle of the surface of the CuMn alloy film is a surface exposed from a contact hole of an insulating layer.

7. A method of manufacturing a thin-film transistor substrate including a thin-film transistor having a CuMn alloy film, the method comprising:

forming the CuMn alloy film; and

controlling a contact resistance of a surface of the CuMn alloy film on a basis of a contact angle of the surface of the CuMn alloy film, wherein

the controlling includes:

measuring the contact angle of the surface of the CuMn alloy film; and

determining whether or not the contact angle which has been measured is less than or equal to a predetermined value.

8. The method of manufacturing the thin-film transistor substrate according to claim 7 , wherein

the predetermined value of the contact angle is 52 degrees.

9. The method of manufacturing the thin-film transistor substrate according to claim 7 , wherein

when the contact angle which has been measured is determined to be greater than the predetermined value in the determining, the controlling further includes cleaning the surface of the CuMn alloy film.

10. The method of manufacturing the thin-film transistor substrate according to claim 9 , wherein

in the cleaning, the surface of the CuMn alloy film is cleaned using an alkali solution.

11. The method of manufacturing the thin-film transistor substrate according to claim 7 , wherein the contact angle is a contact angle with respect to water.

12. The method of manufacturing the thin-film transistor substrate according to claim 7 , wherein the contact angle is between 40 and 65 degrees.

13. The method of manufacturing the thin-film transistor substrate according to claim 7 , further comprising:

depositing an insulating layer on the CuMn alloy film; and

exposing the CuMn surface for a predetermined period of time,

wherein the predetermined period of time is a time period starting from removing a resist film when forming a contact hole through the insulating layer.

14. The method of manufacturing the thin-film transistor substrate according to claim 7 , wherein the contact angle of the surface of the CuMn alloy film is a surface exposed from a contact hole of an insulating layer.

15. A method of manufacturing a thin-film transistor substrate including a thin-film transistor having a CuMn alloy film, the method comprising:

forming the CuMn alloy film; and

controlling a contact resistance of a surface of the CuMn alloy film on a basis of a contact angle of the surface of the CuMn alloy film, wherein

the CuMn alloy film is located in an uppermost layer of each of a source electrode and a drain electrode of the thin-film transistor.

16. The method of manufacturing the thin-film transistor substrate according to claim 15 , wherein the contact angle is a contact angle with respect to water.

17. The method of manufacturing the thin-film transistor substrate according to claim 15 , wherein the contact angle is between 40 and 65 degrees.

18. The method of manufacturing the thin-film transistor substrate according to claim 15 , further comprising:

depositing an insulating layer on the CuMn alloy film; and

exposing the CuMn surface for a predetermined period of time,

wherein the predetermined period of time is a time period starting from removing a resist film when forming a contact hole through the insulating layer.

19. The method of manufacturing the thin-film transistor substrate according to claim 15 , wherein the contact angle of the surface of the CuMn alloy film is a surface exposed from a contact hole of an insulating layer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2016
From: SAITOH, TOHRU
To: JOLED INC.
Reel/Frame 040011/0454 →
Priority Claims (1)
JP 2014-084036 · Apr 15, 2014 · national
Continuity (1)
Related Publication 20170040234A1 · Feb 9, 2017