Thin-film transistor device and display device using same

1. A display device comprising:

a substrate;

a light-emitter disposed on the substrate;

a transistor that drives the light-emitter;

a lead wiring layer pattern, made from metal, that extends from a source, drain, or gate of the transistor to an outer region outside a region in which the light-emitter is present;

a passivation layer in which a contact hole is opened, the passivation layer being disposed covering the lead wiring layer pattern, the contact hole, in plan view, being superimposed over the lead wiring layer pattern in the outer region;

a connecting wiring layer pattern that is continuous across the passivation layer, an inner circumference of the contact hole, and the lead wiring layer pattern in the contact hole;

a lower sealing layer pattern that is electrically conductive, the lower sealing layer pattern being disposed on the connecting wiring layer pattern, covering a portion of the connecting wiring layer pattern in the contact hole;

an upper sealing layer pattern that is electrically conductive, the upper sealing layer pattern being disposed above the connecting wiring layer pattern, covering and in direct contact with a portion of the lower sealing layer pattern in the contact hole; and

a contact prevention layer pattern disposed between the periphery of the lower sealing layer pattern and the upper sealing layer pattern.

2. The display device of claim 1 , further comprising:

a connecting terminal portion for connecting a portion of the connecting wiring layer pattern on the passivation layer to wiring outside the region, wherein

the upper sealing layer pattern extends along the connecting wiring layer pattern to the connecting terminal portion or near the connecting terminal portion.

3. The display device of claim 2 , wherein

the lower sealing layer pattern extends along the connecting wiring layer pattern to the connecting terminal portion or near the connecting terminal portion, and

the contact prevention layer pattern is disposed between the upper sealing layer pattern and the lower sealing layer pattern outside the contact hole.

4. The display device of claim 2 , wherein

the connecting wiring layer pattern extends to a periphery or near the periphery of the substrate, and

the connecting terminal portion is disposed where the connecting wiring layer pattern terminates at the periphery or near the periphery of the substrate.

5. The display device of claim 1 , further comprising:

a connecting terminal portion for connecting a portion of the upper sealing layer pattern on the passivation layer to wiring outside the region, wherein

the connecting wiring layer pattern terminates near the inner circumference of the contact hole.

6. The display device of claim 1 , wherein

the light-emitter and the transistor are provided in plurality,

the lead wiring layer pattern is provided in plurality, and

in a longitudinal direction of each of the lead wiring layer patterns, a location in which the contact hole is superimposed is different for adjacent ones of the lead wiring layer patterns.

7. The display device of claim 1 , wherein

the contact prevention layer pattern is made from insulating material.

8. The display device of claim 7 , wherein

the contact prevention layer pattern includes an upper passivation layer and a planarizing layer on the upper passivation layer.

9. The display device of claim 1 , wherein

the lower sealing layer pattern fills the contact hole and an upper portion of the lower sealing layer pattern protrudes from the contact hole.

10. The display device claim 1 , wherein

in the passivation layer, in a plan view, a plurality of the contact holes is superimposed over the lead wiring layer pattern, and a plurality of the lower sealing layer patterns is disposed therein, the lower sealing layer patterns being separate from each other.

11. The display device of claim 1 , wherein

in the passivation layer, in a plan view, a plurality of the contact holes is superimposed over the lead wiring layer pattern, and the lower sealing layer pattern is continuous across the plurality of the contact holes.

12. The display device of claim 1 , wherein

the lead wiring layer pattern is a layered metal body of layers including a layer including copper or the lead wiring layer pattern is an alloy layer including copper.

13. The display device of claim 1 , wherein

the lower sealing layer pattern is a layered metal body of layers including a layer including copper or the lower sealing layer pattern is an alloy layer including copper.

14. The display device of claim 1 , wherein

the upper sealing layer pattern is a layered metal body consisting of a thin film made from tungsten and a thin film made from aluminum or aluminum alloy.

15. A thin-film transistor device comprising:

a substrate;

a transistor that drives a light-emitter disposed on the substrate;

a lead wiring layer pattern, made from metal, that extends from a source, drain, or gate of the transistor to an outer region outside a region in which the light-emitter is present;

a passivation layer in which a contact hole is opened, the passivation layer being disposed covering the lead wiring layer pattern, the contact hole, in plan view, being superimposed over the lead wiring layer pattern in the outer region;

a connecting wiring layer pattern that is continuous across the passivation layer, an inner circumference of the contact hole, and the lead wiring layer pattern in the contact hole;

a lower sealing layer pattern that is electrically conductive, the lower sealing layer pattern being disposed on the connecting wiring layer pattern, covering a portion of the connecting wiring layer pattern in the contact hole;

an upper sealing layer pattern that is electrically conductive, the upper sealing layer pattern being disposed above the connecting wiring layer pattern, covering and in contact with a portion of the lower sealing layer pattern that, in plan view, is more central than a periphery of the lower sealing layer pattern, and the upper sealing layer pattern directly contacting a portion of the connecting wiring layer pattern; and

a contact prevention layer pattern disposed between the periphery of the lower sealing layer pattern and the upper sealing layer pattern.

16. The thin-film transistor device of claim 15 , further comprising:

a connecting terminal portion for connecting a portion of the connecting wiring layer pattern on the passivation layer to wiring outside the region, wherein

the upper sealing layer pattern extends along the connecting wiring layer pattern to the connecting terminal portion or near the connecting terminal portion.

17. The thin-film transistor device of claim 16 , wherein

the lower sealing layer pattern extends along the connecting wiring layer pattern to the connecting terminal portion or near the connecting terminal portion, and

the contact prevention layer pattern is disposed between the upper sealing layer pattern and the lower sealing layer pattern outside the contact hole.

18. The thin-film transistor device of claim 16 , wherein

the connecting wiring layer pattern extends to a periphery or near the periphery of the substrate, and

the connecting terminal portion is disposed where the connecting wiring layer pattern terminates at the periphery or near the periphery of the substrate.

19. The thin-film transistor device of claim 15 , further comprising:

a connecting terminal portion for connecting a portion of the upper sealing layer pattern on the passivation layer to wiring outside the region, wherein

the connecting wiring layer pattern terminates near the inner circumference of the contact hole.

20. The thin-film transistor device of claim 15 , wherein

the light-emitter and the transistor are provided in plurality,

the lead wiring layer pattern is provided in plurality, and

in a longitudinal direction of each of the lead wiring layer patterns, a location in which the contact hole is superimposed is different for adjacent ones of the lead wiring layer patterns.

21. The thin-film transistor device of claim 15 , wherein

the contact prevention layer pattern is made from insulating material.

22. The thin-film transistor device of claim 21 , wherein

the contact prevention layer pattern includes an upper passivation layer and a planarizing layer on the upper passivation layer.

23. The thin-film transistor device of claim 15 , wherein

the lower sealing layer pattern fills the contact hole and an upper portion of the lower sealing layer pattern protrudes from the contact hole.

24. The thin-film transistor device of claim 15 , wherein

in the passivation layer, in a plan view, a plurality of the contact holes is superimposed over the lead wiring layer pattern, and a plurality of the lower sealing layer patterns is disposed therein, the lower sealing layer patterns being separate from each other.

25. The thin-film transistor device of claim 15 , wherein

in the passivation layer, in a plan view, a plurality of the contact holes is superimposed over the lead wiring layer pattern, and the lower sealing layer pattern is continuous across the plurality of the contact holes.

26. The thin-film transistor device of claim 15 , wherein

the lead wiring layer pattern is a layered metal body of layers including a layer including copper or the lead wiring layer pattern is an alloy layer including copper.

27. The thin-film transistor device of claim 15 , wherein

the lower sealing layer pattern is a layered metal body of layers including a layer including copper or the lower sealing layer pattern is an alloy layer including copper.

28. The thin-film transistor device of claim 15 , wherein

the upper sealing layer pattern is a layered metal body consisting of a thin film made from tungsten and a thin film made from aluminum or aluminum alloy.