IP Library Granted Patent US 10,121,898
Granted Patent B2
US 10,121,898 · App. 15/309,794 · Granted Nov 6, 2018

Thin-film transistor substrate and method of manufacturing the same

Inventor: Yuta Sugawara (Tokyo, JP)
Assignee: JOLED INC.
H01L29/78606H01L21/02164H01L21/02178H01L21/02233H01L21/02252H01L21/02565H01L21/02592H01L27/127H01L27/1225H01L29/247H01L29/78693H01L27/3262
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Quick Facts
Patent No.
US 10,121,898
App. No.
15/309,794
Granted
Nov 6, 2018
Kind
B2
Abstract

A method of manufacturing a TFT substrate includes the steps of forming an oxide semiconductor layer above a substrate, forming a first oxide film on the oxide semiconductor layer, performing oxidation processing on the oxide semiconductor layer after formation of the first oxide film, and forming a second oxide film on the first oxide film after the oxidation processing.

Claims (58)

1. A thin-film transistor substrate manufactured by a method comprising:

forming an oxide semiconductor layer above a substrate;

forming a first oxide film on the oxide semiconductor layer;

performing oxidation processing on the oxide semiconductor layer after formation of the first oxide film, wherein a duration of the oxidation processing increases with a film deposition temperature of the first oxide film; and

forming a second oxide film on the first oxide film after the oxidation processing,

wherein in concentration profiles of elements in a direction of lamination,

a concentration profile of fluorine elements shows a peak in proximity to a boundary between the first oxide film and the second oxide film,

a concentration profile of nitric oxide shows that a concentration in proximity to the boundary is higher than a concentration in proximity to a center of the second oxide film, and

a concentration profile of hydrogen elements discontinuously changes in proximity to the boundary.

2. The thin-film transistor substrate according to claim 1 ,

wherein a film deposition temperature of the first oxide film is 270° C. or higher.

3. The thin-film transistor substrate according to claim 2 ,

wherein a duration of the oxidation processing increases with a film thickness of the first oxide film.

4. The thin-film transistor substrate according to claim 1 ,

wherein a duration of the oxidation processing increases with a film thickness of the first oxide film.

5. The thin-film transistor substrate according to claim 1 ,

wherein the first oxide film has a film thickness that is greater than or equal to 5 nm and less than or equal to 40 nm.

6. The thin-film transistor substrate according to claim 1 ,

wherein a duration of the oxidation processing increases with a film deposition temperature of the second oxide film.

7. The thin-film transistor substrate according to claim 1 ,

wherein the oxidation processing includes plasma treatment.

8. The thin-film transistor substrate according to claim 7 ,

wherein the plasma treatment is performed using a nitrous oxide gas for a period of time that is greater than or equal to 5 seconds and less than or equal to 300 seconds.

9. The thin-film transistor substrate according to claim 1 ,

wherein the first oxide film and the second oxide film are silicon oxide films.

10. The thin-film transistor substrate according to claim 1 ,

wherein the oxide semiconductor layer is a transparent amorphous oxide semiconductor.

11. The thin-film transistor substrate according to claim 1 ,

wherein the oxide semiconductor layer is InGaZnO.

12. A thin-film transistor substrate comprising:

a substrate;

an oxide semiconductor layer;

a first oxide film; and

a second oxide film,

the oxide semiconductor layer, the first oxide film, and the second oxide film being sequentially laminated above the substrate,

wherein in concentration profiles of elements in a direction of lamination,

a concentration profile of fluorine elements shows a peak in proximity to a boundary between the first oxide film and the second oxide film,

a concentration profile of nitric oxide shows that a concentration in proximity to the boundary is higher than a concentration in proximity to a center of the second oxide film, and

a concentration profile of hydrogen elements discontinuously changes in proximity to the boundary.

13. A thin-film transistor substrate manufactured by a method comprising:

forming an oxide semiconductor layer above a substrate;

forming a first oxide film on the oxide semiconductor layer;

performing oxidation processing on the oxide semiconductor layer after formation of the first oxide film; and

forming a second oxide film on the first oxide film after the oxidation processing, wherein a film deposition temperature of the second oxide film is the same as a temperature during the oxidation processing,

wherein in concentration profiles of elements in a direction of lamination,

a concentration profile of fluorine elements shows a peak in proximity to a boundary between the first oxide film and the second oxide film,

a concentration profile of nitric oxide shows that a concentration in proximity to the boundary is higher than a concentration in proximity to a center of the second oxide film, and

a concentration profile of hydrogen elements discontinuously changes in proximity to the boundary.

14. The thin-film transistor substrate according to claim 13 ,

wherein the oxidation processing includes plasma treatment.

15. The thin-film transistor substrate according to claim 14 ,

wherein the plasma treatment is performed using a nitrous oxide gas for a period of time that is greater than or equal to 5 seconds and less than or equal to 300 seconds.

16. The thin-film transistor substrate according to claim 13 ,

wherein the first oxide film and the second oxide film are silicon oxide films.

17. The thin-film transistor substrate according to claim 13 ,

wherein the oxide semiconductor layer is a transparent amorphous oxide semiconductor.

18. The thin-film transistor substrate according to claim 13 ,

wherein the oxide semiconductor layer is InGaZnO.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2016
From: SUGAWARA, YUTA
To: JOLED INC.
Reel/Frame 040259/0361 →
Priority Claims (1)
JP 2014-098127 · May 9, 2014 · national
Continuity (1)
Related Publication 20170250289A1 · Aug 31, 2017
Cited By (1)
US 12,660,525