IP Library Granted Patent US 10,448,923
Granted Patent B2
US 10,448,923 · App. 15/315,696 · Granted Oct 22, 2019

Amplifier circuit and ultrasonic probe

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Quick Facts
Patent No.
US 10,448,923
App. No.
15/315,696
Granted
Oct 22, 2019
Kind
B2
Abstract

Amplification of a signal by a small circuit size and reduction of a power are achieved. A current controlling current source unit 53 changes an outputting current based on a transition time setting signal tp. A current controlling current source unit 54 changes a drawing current based on a transition time setting signal tn. An amplitude control unit 55 changes a power source voltage supplied to the current controlling current source unit 53 and changes amplitude of a voltage generated by a current outputted from the current controlling current source unit 53 , based on amplitude setting signal ap. An amplitude control unit 56 changes a power source voltage supplied to the current controlling current source unit 54 and changes amplitude of a voltage generated by the current drawn by the current controlling current source unit 54 , based on amplitude setting signal an. The buffer unit 57 drives a load in accordance with the current outputted from the current controlling current source unit 53 and the current drawn from the current controlling current source unit 54.

Claims (58)

1. An amplifier circuit comprising:

a first current source unit for changing an outputting current based on a first setting signal;

a second current source unit for changing a drawing current based on a second setting signal;

a first amplitude control unit for changing a power source voltage supplied to the first current source unit and changing amplitude of a voltage generated by the current outputted from the first current source unit based on a third setting signal;

a second amplitude control unit for changing a power source voltage supplied to the second current source unit and changing amplitude of a voltage generated by the current drawn by the second current source unit based on a fourth setting signal;

a buffer unit for driving a load in accordance with the current outputted from the first current source unit and the current drawn from the second current source unit;

a third current source unit inputted with the first setting signal, outputting a first setting current in accordance with a magnitude of the first setting signal, inputted with the second setting signal, and outputting a second setting current in accordance with a magnitude of the second setting signal,

wherein the first current source unit changes the current outputted based on the magnitude of the first setting current outputted from the third current source unit,

wherein the second current source unit changes the current drawn based on the magnitude of the second setting current outputted from the third current source unit,

wherein the first current source unit and the second current source unit are connected in series,

wherein the first amplitude control unit is connected to a first polarity of a power source and the first current source unit, changes the power source voltage supplied to the first current source unit, and supplies a current outputted by the first current source unit from the power source,

wherein the second amplitude control unit is connected between a second polarity of the power source and the second current source unit, changes the power source voltage supplied to the second current source unit, and makes the current drawn by the second current source unit flow to the power source, and

wherein the buffer unit is connected between the first polarity and the second polarity of the power source, and an input is connected between the first current source unit and the second current source unit connected in series.

2. The amplifier circuit according to claim 1 ,

wherein the third current source unit is supplied with a voltage from a low voltage current source lower than the power source.

3. An amplifier circuit comprising:

a first current source unit for changing an outputting current based on a first setting signal;

a second current source unit for changing a drawing current based on a second setting signal;

a first amplitude control unit for changing a power source voltage supplied to the first current source unit and changing amplitude of a voltage generated by the current outputted from the first current source unit based on a third setting signal;

a second amplitude control unit for changing a power source voltage supplied to the second current source unit and changing amplitude of a voltage generated by the current drawn by the second current source unit based on a fourth setting signal;

a buffer unit for driving a load in accordance with the current outputted from the first current source unit and the current drawn from the second current source unit; and

a converging circuit for converging a voltage of an input of the buffer unit to a reference voltage when the first current source unit finishes outputting the current and when the second current source unit finishes drawing the current.

4. An amplifier circuit comprising:

a first current source unit for changing an outputting current based on a first setting signal;

a second current source unit for changing a drawing current based on a second setting signal;

a first amplitude control unit for changing a power source voltage supplied to the first current source unit and changing amplitude of a voltage generated by the current outputted from the first current source unit based on a third setting signal;

a second amplitude control unit for changing a power source voltage supplied to the second current source unit and changing amplitude of a voltage generated by the current drawn by the second current source unit based on a fourth setting signal; and

a buffer unit for driving a load in accordance with the current outputted from the first current source unit and the current drawn from the second current source unit,

wherein the first current source unit includes a first transistor circuit for outputting the current in accordance with a magnitude of the first setting signal,

wherein the second current source unit includes a second transistor circuit for drawing the current in accordance with a magnitude of the second setting signal,

wherein the first amplitude control unit includes a first transistor a drain of which is connected to a first polarity of a power source, a source of which is connected to the first transistor circuit, and a gate of which is inputted with the third setting signal,

wherein the second amplitude control unit includes a second transistor a drain of which is connected to a second polarity of the power source, a source of which is connected to the second transistor, and a gate of which is inputted with the fourth setting signal,

wherein the buffer unit includes a third transistor in which the buffer unit includes a third transistor outputting a current from the first polarity of the power source to the load in accordance with the current outputted from the first transistor circuit, and a fourth transistor drawing a current from the load to the second polarity of the power source in accordance with the current drawn from the second transistor circuit, and

wherein sizes of the transistor configuring the first transistor circuit, the transistor configuring the second transistor circuit, the first transistor, and the second transistor are smaller than sizes of the third transistor and the fourth transistor.

5. An amplifier circuit comprising:

a first current source unit for changing an outputting current based on a first setting signal;

a second current source unit for changing a drawing current based on a second setting signal;

a first amplitude control unit for changing a power source voltage supplied to the first current source unit and changing amplitude of a voltage generated by the current outputted from the first current source unit based on a third setting signal;

a second amplitude control unit for changing a power source voltage supplied to the second current source unit and changing amplitude of a voltage generated by the current drawn by the second current source unit based on a fourth setting signal;

a buffer unit for driving a load in accordance with the current outputted from the first current source unit and the current drawn from the second current source unit,

wherein the first current source unit includes a first transistor circuit for outputting the current in accordance with a magnitude of the first setting signal,

wherein the second current source unit includes a second transistor circuit for drawing the current in accordance with a magnitude of the second setting signal,

wherein the first amplitude control unit includes a first transistor a drain of which is connected to a first polarity of a power source, a source of which is connected to the first transistor circuit, and a gate of which is inputted with the third setting signal,

wherein the second amplitude control unit includes a second transistor a drain of which is connected to a second polarity of the power source, a source of which is connected to the second transistor, and a gate of which is inputted with the fourth setting signal, and

wherein the buffer unit includes a third transistor in which the buffer unit includes a third transistor outputting a current from the first polarity of the power source to the load in accordance with the current outputted from the first transistor circuit, and a fourth transistor drawing a current from the load to the second polarity of the power source in accordance with the current drawn from the second transistor circuit;

a fifth transistor a gate of which is inputted with the first setting signal, and which outputs a first setting current in accordance with a magnitude of a voltage of the first setting signal to the first transistor circuit;

a sixth transistor a gate of which is inputted with the second setting signal and which outputs a second setting current in accordance with a magnitude of a voltage of the second setting signal to the second transistor circuit;

a seventh transistor for shifting a level of the first setting current outputted from the fifth transistor; and

an eighth transistor for shifting a level of the second setting current outputted from the sixth transistor.

6. The amplifier circuit according to claim 5 ,

wherein sizes of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are smaller than sizes of the third transistor and the fourth transistor.

7. An ultrasonic probe comprising:

a first current source unit for changing an outputting current based on a first setting signal;

a second current source unit for changing a drawing current based on a second setting signal;

a first amplitude control unit for changing a power source voltage supplied to the current source unit, and changing amplitude of a voltage generated by a current outputted from the first current source unit based on a third setting signal;

a second amplitude control unit for changing a power source voltage supplied to the second current source unit, and changing amplitude of a voltage generated by a current drawn by the second current source unit based on a fourth setting signal;

a buffer unit for driving an oscillator emitting an ultrasonic wave in accordance with the current outputted form the first current source unit and the current drawn from the second current source unit; and

a converging circuit for converging a voltage of an input of the buffer unit to a reference voltage when the first current source unit finishes outputting the current and when the second current source unit finishes drawing the current.

Assignments (5)
MERGER Recorded Jan 10, 2025
From: FUJIFILM HEALTHCARE CORPORATION
To: FUJIFILM CORPORATION
Reel/Frame 069869/0916 →
MERGER Recorded Oct 11, 2024
From: FUJIFILM HEALTHCARE CORPORATION
To: FUJIFILM CORPORATION
Reel/Frame 070608/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE PROPERTY AND APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 058026 FRAME: 0559. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 31, 2022
From: HITACHI LTD.
To: FUJIFILM HEALTHCARE CORPORATION
Reel/Frame 058917/0853 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2021
From: HITACHI, LTD.
To: FUJIFILM HEALTHCARE CORPORATION
Reel/Frame 058026/0559 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2016
From: NISHIMOTO, TAKUMA; IGARASHI, YUTAKA; KATSUBE, YUSAKU; IMAGAWA, KENGO
To: HITACHI, LTD.
Reel/Frame 040815/0641 →