IP Library Granted Patent US 9,852,848
Granted Patent B2
US 9,852,848 · App. 15/317,545 · Granted Dec 26, 2017

COG dielectric composition for use with nickel electrodes

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Quick Facts
Patent No.
US 9,852,848
App. No.
15/317,545
Granted
Dec 26, 2017
Kind
B2
Abstract

Multilayer ceramic chip capacitors which satisfy COG requirements and which are compatible with reducing atmosphere sintering conditions so that non-noble metals such as nickel and nickel alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers comprise a barium strontium zirconate matrix doped with other metal oxides such as TiO 2 , CaO, B 2 O 3 , and MgO in various combinations.

Claims (64)

1. A composition comprising a mixture of precursors that, upon firing, forms a dielectric material comprising:

from about 26.5 wt % to about 34.0 wt % BaO;

from about 18.0 wt % to about 24.5 wt % SrO;

from about 41.0 wt % to about 50.0 wt % ZrO 2 ;

from about 0.50 wt % to about 1.50 wt % CaO; and

from about 0.70 wt % to about 2.50 wt % TiO 2 .

2. The composition according to claim 1 , further comprising precursors such that upon firing the dielectric material further comprises:

from about 0.01 to about 1.0 wt % B 2 O 3 ; and

from about 0.01 to about 1.47 wt % MgO.

3. A lead-free and cadmium-free dielectric paste comprising a solids portion wherein the solids portion comprises the dielectric material of claim 1 .

4. The lead-free and cadmium-free dielectric paste of claim 3 , wherein the solids portion further comprises at least one selected from the group consisting of:

from about 0.01 to about 1.0 wt % B 2 O 3 ;

from about 0.01 to about 1.47 wt % MgO;

from about 0.01 to about 1.78 wt % H 3 BO 3 ; and

from about 0.01 to about 2.14 wt % Mg(OH) 2 .

5. A method of forming an electronic component comprising:

applying the dielectric paste of claim 4 to a substrate; and

firing the substrate at a temperature sufficient to sinter the dielectric paste.

6. The method of claim 5 , wherein the firing is conducted at a temperature of from about 1200° C. to about 1350° C.

7. A multilayer ceramic chip capacitor comprising a fired collection of alternately stacked:

layers of the dielectric paste of claim 4 ; and

layers of an internal electrode material comprising a transition metal other than Ag, Au, Pd, or Pt.

8. The multilayer ceramic chip capacitor of claim 7 , wherein the internal electrode material comprises nickel.

9. A method of forming an electronic component comprising:

alternately applying layers of

the dielectric paste of claim 4 , to form at least one dielectric layer and

a metal-containing electrode paste, to form at least one internal electrode layer

onto a substrate to form a laminar stack;

cutting the laminar stack to a predetermined shape;

separating the cut stack from the substrate; and

firing the stack to densify the metal in the electrode paste and sinter the dielectric paste, wherein the internal electrode layer and the dielectric layer each have a layer thickness.

10. The method of claim 9 , wherein the firing is conducted at a temperature of from about 1200° C. to about 1350° C.

11. The method of claim 9 , wherein the firing is conducted in an atmosphere having a partial oxygen pressure of about 10 −12 atm to about 10 −8 atm.

12. A lead-free and cadmium-free dielectric composition comprising:

from about 47.8 wt % to about 61.3 wt % BaZrO 3 ;

from about 39.4 wt % to about 53.6 wt % SrZrO 3 ;

from about 1.2 wt % to about 3.6 wt % CaTiO 3 ;

from about 0.1 wt % to about 2.14 wt % Mg(OH) 2 ; and

from about 0.1 wt % to about 1.78 wt % H 3 BO 3 .

13. A lead-free and cadmium-free dielectric paste comprising a solids portion wherein the solids portion comprises:

from about 47.8 wt % to about 61.3 wt % BaZrO 3 ;

from about 39.4 wt % to about 53.6 wt % SrZrO 3 ;

from about 1.2 wt % to about 3.6 wt % CaTiO 3 ;

from about 0.1 wt % to about 2.14 wt % Mg(OH) 2 ; and

from about 0.1 wt % to about 1.78 wt % H 3 BO 3 .

14. A method of forming an electronic component comprising:

applying the dielectric paste of claim 13 to a substrate; and

firing the substrate at a temperature sufficient to sinter the dielectric paste.

15. The method of claim 14 , wherein the firing is conducted at a temperature of from about 1200° C. to about 1350° C.

16. The method of claim 14 , wherein the firing is conducted in an atmosphere having a partial oxygen pressure of about 10 −12 atm to about 10 −8 atm.

17. A multilayer ceramic chip capacitor comprising a fired collection of: alternately stacked:

layers of the dielectric paste of claim 13 ; and

layers of an internal electrode material comprising a transition metal other than Ag, Au, Pd, or Pt.

18. The multilayer ceramic chip capacitor of claim 17 , wherein the internal electrode material comprises nickel.

19. A method of forming an electronic component comprising:

alternately applying layers of

a dielectric material comprising the paste of claim 13 to form at least one dielectric layer and

a metal-containing electrode paste to form at least one internal electrode layer

onto a substrate to form a laminar stack;

cutting the laminar stack to a predetermined shape;

separating the cut stack from the substrate; and

firing the stack to densify the metal in the electrode paste and sinter the dielectric paste, wherein the at least one internal electrode layer and the at least one dielectric layer each have a layer thickness.

20. The method of claim 19 , wherein the firing is conducted at a temperature of from about 1200° C. to about 1350° C.

21. The method of claim 19 , wherein the firing is conducted in an atmosphere having a partial oxygen pressure of about 10 −12 atm to about 10 −8 atm.

Assignments (4)
SECURITY INTEREST Recorded May 2, 2022
From: CHROMAFLO TECHNOLOGIES CORPORATION; FERRO CORPORATION; FERRO ELECTRONIC MATERIALS INC.; PRINCE ENERGY LLC; PRINCE MINERALS LLC; PRINCE SPECIALTY PRODUCTS LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS ADMINISTRATIVE AGENT
Reel/Frame 059845/0082 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT R/F 041736/0178 Recorded Apr 21, 2022
From: PNC BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: FERRO CORPORATION
Reel/Frame 059747/0129 →
SECURITY INTEREST Recorded Feb 16, 2017
From: FERRO CORPORATION
To: PNC BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 041736/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: SYMES, WALTER J., JR.; MEGHERHI, MOHAMMED H.
To: FERRO CORPORATION
Reel/Frame 040732/0222 →