Pixel arrangement

1. A pixel arrangement comprising:

a plurality of pixels arranged adjacent to each other; and

a substrate configured to receive the plurality of pixels,

wherein each pixel of the plurality of pixels comprises:

a plurality of optical cells electrically coupled to each other; and

an electrical interconnection electrically isolated from the plurality of optical cells, the electrical interconnection arranged to provide electrical communication between two separate conducting terminals external to the pixel; and wherein each pixel of the plurality of pixels and a neighbouring pixel of the plurality of pixels are of different orientations with respect to each other.

2. The pixel arrangement of claim 1 , wherein for each pixel of the plurality of pixels, the electrical interconnection in entirety is arranged on the pixel.

3. The pixel arrangement of claim 1 , wherein each pixel of the plurality of pixels further comprises a pixel substrate on which the plurality of optical cells are arranged.

4. The pixel arrangement of claim 3 , wherein the electrical interconnection comprises a planar electrical interconnection arranged on the pixel substrate.

5. The pixel arrangement of claim 3 , wherein the plurality of optical cells and the electrical interconnection are arranged on a same surface of the pixel substrate.

6. The pixel arrangement of claim 1 , wherein the substrate comprises a chip carrier having at least one conducting pad.

7. The pixel arrangement of claim 6 , wherein the electrical interconnection of one pixel of the plurality of pixels is electrically coupled to at least one of an electrical interconnection of another pixel of the plurality of pixels, or an electrode of another pixel of the plurality of pixels, or the at least one conducting pad of the chip carrier.

8. The pixel arrangement of claim 6 , wherein the electrical interconnection of one pixel of the plurality of pixels is coupled using wire-bonding to at least one of an electrical interconnection of another pixel of the plurality of pixels, or an electrode of another pixel of the plurality of pixels, or the at least one conducting pad of the chip carrier.

9. The pixel arrangement of claim 1 , wherein each pixel of the plurality of pixels comprises a polygon-shaped pixel.

10. The pixel arrangement of claim 9 , wherein the electrical interconnection extends along at least two adjacent sides of the polygon-shaped pixel.

11. The pixel arrangement of claim 1 , wherein each pixel of the plurality of pixels further comprises a first electrode electrically coupled to one end of each of the plurality of optical cells, and a second electrode electrically coupled to the opposite end of each of the plurality of optical cells.

12. The pixel arrangement of claim 11 , wherein the first electrode and the second electrode are arranged away from the electrical interconnection.

13. The pixel arrangement of claim 1 , wherein for each pixel of the plurality of pixels, the electrical interconnection is spaced apart from the plurality of optical cells.

14. The pixel arrangement of claim 1 , wherein the electrical interconnection comprises at least two bonding pads.

15. The pixel arrangement of claim 1 , wherein the plurality of optical cells are electrically coupled to each other in parallel.

16. The pixel arrangement of claim 1 , wherein each of the plurality of optical cells comprises an avalanche photo diode (APD) and a quenching resistor.

17. The pixel arrangement of claim 1 , wherein the plurality of pixels are in a side-by-side arrangement.

18. The pixel arrangement of claim 1 , wherein each pixel of the plurality of pixels has at least one side in contact with at least one side of a neighbouring pixel of the plurality of pixels.

19. The pixel arrangement of claim 1 , wherein each pixel of the plurality of pixels and a neighbouring pixel of the plurality of pixels are spaced apart from each other with a gap of less than 0.1 μm.