IP Library Granted Patent US 10,290,598
Granted Patent B2
US 10,290,598 · App. 15/323,521 · Granted May 14, 2019

Method and apparatus for forming backside die planar devices and saw filter

Inventors: Kevin J. Lee (Beaverton, OR); Ruchir Saraswat (Swindon, GB); Uwe Zillmann (Braunschweig, DE); Nicholas P. Cowley (Wroughton, GB); Richard J. Goldman (Cirencester, GB)
Assignee: Intel Corporation
H01L24/09G06F1/16H01F27/2804H01L23/481H01L23/5226H01L23/5227H01L23/645H01L23/66H01L24/17H03H7/42H03H9/64H01L23/525H01L24/05H01L24/06H01L24/13H01L24/16H01L2223/6616H01L2223/6661H01L2223/6677H01L2224/0233H01L2224/02372H01L2224/02375H01L2224/02379H01L2224/0401H01L2224/05548H01L2224/16146H01L2224/16225H01L2224/17181
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Quick Facts
Patent No.
US 10,290,598
App. No.
15/323,521
Granted
May 14, 2019
Kind
B2
Abstract

Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

Claims (40)

1. An apparatus comprising:

a backside of a first die having a redistribution layer (RDL);

one or more passive planar devices on the backside, the one or more passive planar devices formed in the RDL;

a front-side of the first die having an active region;

one or more vias to couple the active region with the one or more passive planar devices, wherein the one or more vias include ground and signal vias; and

a layer comprising piezoelectric material, wherein the layer is on the backside of the first die such that the layer is disposed on the RDL.

2. The apparatus of claim 1 comprises a second die coupled to the backside of the first die.

3. The apparatus of claim 2 , wherein the second die includes an active region coupled to the one or more passive planar devices of the first die.

4. The apparatus of claim 1 comprises a passivation layer on the layer.

5. The apparatus of claim 1 , wherein the one or more passive planar devices is one or more of:

a SAW filter;

a band-pass filter;

a low-pass filter;

a high-pass filter;

an inductor;

an antenna; or

a balun.

6. The apparatus of claim 1 comprises bumps on the backside of the die to couple the one or more passive planar devices to another die.

7. An apparatus comprising:

a backside of a die having a redistribution layer (RDL);

one or more SAW filters on the backside, the one or more SAW filters in the RDL;

a piezoelectric layer on the RDL over the one or more SAW filters;

a front-side of the die having an active region; and

one or more vias to couple the active region with the one or more SAW filters.

8. The apparatus of claim 7 , wherein the active region comprises a low noise amplifier (LNA) coupled to one of the one or more SAW filters.

9. The apparatus of claim 7 , wherein the active region comprises a power amplifier (PA) coupled to one of the one or more SAW filters.

10. The apparatus of claim 7 further comprises one or more passive planar devices on the backside.

11. A system comprising:

a memory;

a processor die coupled to the memory, the processor die having:

a backside with a redistribution layer (RDL);

one or more passive planar devices on the backside, the one or more passive planar devices formed in the RDL;

a front-side of the first die having an active region; and

one or more vias to couple the active region with the one or more passive planar device;

a layer comprising piezoelectric material, wherein the layer is on the backside of the first die such that the layer is on the RDL; and

a wireless interface to allow the processor to communicatively couple with another device.

12. The system of claim 11 comprises a display interface for displaying content processed by the processor.

13. The system of claim 11 , wherein the active region comprises a low noise amplifier (LNA) coupled to one of the one or more passive planar devices.

14. The system of claim 13 , wherein the one or more vias include ground and signal vias.

15. The system of claim 11 comprises another die coupled to the backside of the processor die.

Continuity (1)
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Cited By (1)
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