Via etch method for back contact multijunction solar cells
This disclosure relates to semiconductor devices and methods for fabricating semiconductor devices. Particularly, the disclosure relates to back-contact-only multijunction solar cells and the process flows for making such solar cells, including a wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers.
1. A through-wafer via structure, comprising:
a substrate having a front substrate surface and a back substrate surface;
a plurality of heteroepitaxial layers overlying the front substrate surface, wherein the plurality of heteroepitaxial layers has a top surface;
an anti-reflection coating overlying a first portion of the plurality of heteroepitaxial layers;
a patterned cap region overlying and electrically connected to a second portion of the plurality of heteroepitaxial layers, wherein the patterned cap region has a top surface;
a front surface contact overlying and electrically connected to the patterned cap region, wherein
the front surface contact has a bottom surface; and
the bottom surface of the front surface contact lies between the top surface of the patterned cap region and the top surface of the plurality of heteroepitaxial layers; and
a through-wafer via interconnecting a front surface solder pad and the front surface contact, wherein, the through-wafer via comprises:
a side wall;
a passivation layer lining the sidewall and contacting the front surface contact; and
a metal layer underlying the passivation layer and directly contacting the bottom surface of the front surface contact within the through-wafer via.
2. The through-wafer via structure of claim 1 , wherein the plurality of heteroepitaxial layers comprises at least two junctions of a multijunction solar cell.
3. The through-wafer via structure of claim 1 , wherein:
a first portion of the anti-reflection coating overlies the first portion of the plurality of heteroepitaxial layers;
the patterned cap region overlies the second portion of the plurality of heteroepitaxial layers;
a second portion of the anti-reflection coating overlies a third portion of the plurality of heteroepitaxial layers, wherein the third portion of the plurality of heteroepitaxial layers is within the patterned cap region; and
the metal layer plugs the bottom of the through-wafer via;
and further comprising:
a metal overlying the metal layer and filling the through-wafer via; wherein the front surface contact overlies the second portion of the anti-reflection coating and the patterned cap region and the through-wafer via extends from the back substrate surface through the second portion of the anti-reflection coating.
4. The through-wafer via structure of claim 1 , wherein the second portion of the anti-reflection coating is located between a portion of the front surface contact and the plurality of heteroepitaxial layers.
5. The through-wafer via structure of claim 1 , wherein the second portion of the anti-reflection coating is located between the through-wafer via and the patterned cap region.
6. A semiconductor device comprising a plurality of the through-wafer via structures of claim 1 .
7. The semiconductor device of claim 6 , wherein the semiconductor device is characterized by a unit mass per area of less than 0.09 g/cm 2 .
8. A method of fabricating a through-wafer via structure, comprising:
providing a semiconductor wafer, wherein the semiconductor wafer comprises:
a substrate comprising a front substrate surface and a back substrate surface;
a plurality of heteroepitaxial layers overlying the front substrate surface, wherein the plurality of heteroepitaxial layers has a top surface;
an anti-reflection coating overlying a first portion of the plurality of heteroepitaxial layers;
a patterned cap region overlying and electrically connected to a second portion of the plurality of heteroepitaxial layers, wherein the patterned cap region has a top surface;
a front surface contact overlying and electrically connected to the patterned cap region and having a bottom surface;
wherein the bottom surface of the front surface contact lies between the top surface of the patterned cap region and the top surface of the plurality heteroepitaxial layers;
an optical adhesive overlying the front surface contact and the plurality of heteroepitaxial layers; and
a coverglass overlying the optical adhesive layer;
forming a through-wafer via interconnecting the front surface contact to a front contact pad underlying the back substrate surface wherein forming the through-wafer via includes etching the back surface of the substrate to expose the bottom surface of the front surface contact; and
depositing a passivation layer on sidewalls of the through-wafer via; and depositing a metal layer within the through-wafer via underlying the passivation layer which directly contacts the bottom surface of the front surface contact.
9. The method of claim 8 , wherein forming a through-wafer via comprises wet etching the substrate and the plurality of heteroepitaxial layers using an etchant mixture comprising iodic acid, hydrofluoric acid, and water.
10. The method of claim 8 , further comprising forming a back surface contact interconnected to the back substrate surface.
11. The method of claim 8 , further comprising thinning the substrate to a thickness less than 150 μm, wherein thinning the substrate comprises wet etching, back-grinding, lift-off, or any combination of any of the foregoing.
12. The method of claim 8 , wherein the plurality of heteroepitaxial layers comprises at least two junctions of a multijunction solar cell.
13. The through-wafer via structure of claim 1 , wherein the anti-reflection coating does not overly the front surface contact.
14. The through-wafer via structure of claim 1 , wherein the sidewall comprises trace iodine.
15. The through-wafer via structure of claim 1 , wherein the sidewall is without pitting and undercutting.
16. The through-wafer via structure of claim 1 , wherein the sidewall is characterized by a smooth curved profile, having a smooth surface without undercutting of a junction region compared to other junction regions.
17. The through-wafer via structure of claim 1 , wherein the substrate has a thickness less than 150 μm.