Nonvolatile semiconductor memory device and control method thereof
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.
1. A memory device, comprising:
a memory cell array including a first memory string and a second memory string, the first memory string including first memory cells and a first select transistor, the second memory string including second memory cells and a second select transistor;
a plurality of word lines coupled to the first memory string and the second memory string; and
a control unit configured to perform a first read operation and a second read operation sequentially responsive to the memory device receiving a command and an address, the address including a word line address, a string address, and a block address,
wherein a first voltage is applied to a selected word line and a second voltage is applied to at least one of non-selected word lines during the first and second read operations without making either of the first or second voltages zero voltage, and
wherein the first select transistor is turned on when the first memory string is selected and the second select transistor is turned on when the second memory string is selected.
2. The memory device according to claim 1 , wherein the memory device receives the address after receiving a first command, and the memory device executes the first read operation for the address after receiving a second command.
3. The memory device according to claim 2 , wherein the memory device is configured to output a busy signal after receiving the first command, the address, and the second command.
4. The memory device according to claim 3 , wherein the memory device executes the second read operation for an address which is different from the address received after the first command when the memory device receives a third command.
5. The memory device according to claim 4 , wherein the memory device outputs data of the first read operation and a ready signal after receiving the third command.
6. The memory device according to claim 5 , wherein the memory device outputs a busy signal responsive to the memory device receiving the third command again.
7. The memory device according to claim 6 , wherein the memory device discharges the first or second voltages responsive to the memory device receiving a fourth command while outputting the ready signal.
8. The memory device according to claim 7 , wherein the address includes an address of a lower page or upper page.
9. The memory device according to claim 7 , wherein the control unit is configured to perform an erase operation per block.
10. The memory device according to claim 4 , wherein the memory device changes an address to be accessed responsive to the memory device receiving the third command.
11. The memory device according to claim 4 , wherein the memory device changes a page address to be accessed responsive to the memory device receiving the third command, the page address including a lower page address and an upper page address.
12. A memory device, comprising:
a memory cell array including a first memory string and a second memory string, the first memory string including first memory cells and a first select transistor, the second memory string including second memory cells and a second select transistor,
a plurality of word lines coupled to the first memory string and the second memory string; and
a control unit configured to perform a first read operation and a second read operation sequentially responsive to the memory device receiving a command,
wherein a first voltage is applied to a selected word line and a second voltage is applied to at least one of non-selected word lines during the first and second read operations without making either of the first or second voltages zero voltage, and
wherein the first select transistor is turned on when the first memory string is selected and the second select transistor is turned on when the second memory string is selected.
13. The memory device according to claim 12 , wherein the memory device receives an address after receiving a first command, and the memory device executes the first read operation for the address after receiving a second command.
14. The memory device according to claim 13 , wherein the memory device is configured to output a busy signal after receiving the first command, the address, and the second command.
15. The memory device according to claim 14 , wherein the memory device executes the second read operation for an address which is different from the address received after the first command responsive to the memory device receiving a third command.
16. The memory device according to claim 15 , wherein the memory device outputs data of the first read operation and a ready signal after receiving the third command.
17. The memory device according to claim 16 , wherein the memory device outputs a busy signal responsive to the memory device receiving the third command again.
18. The memory device according to claim 17 , wherein the memory device discharges the first or second voltages responsive to the memory device receiving a fourth command while outputting the ready signal.
19. The memory device according to claim 15 , wherein the memory device changes an address to be accessed responsive to the memory device receiving the third command.
20. The memory device according to claim 15 , wherein the memory device changes a page address to be accessed responsive to the memory device receiving the third command, the page address including a lower page address and an upper page address.
21. A memory device, comprising:
a memory cell array including a first memory string and a second memory string, the first memory string including first memory cells and a first select transistor, the second memory string including second memory cells and a second select transistor;
a plurality of word lines coupled to the first memory string and the second memory string; and
a control unit configured to perform a first read operation and a second read operation sequentially responsive to the memory device receiving a command and an address, the address including a word line address, a string address, and a block address,
wherein a first voltage is applied to a selected word line and a second voltage is applied to at least one of non-selected word lines during the first and second read operations, the control unit being configured to zero out voltages of the selected word line and the one of the non-selected word line during a first period that includes a period of the first read operation and a period of the second read operation.
22. The memory device according to claim 21 , wherein a third voltage is applied to the first select transistor and a fourth voltage which is lower than the third voltage is applied to the second select transistor during the first read operation, a fifth voltage is applied to the first select transistor and a sixth voltage which is higher than the third voltage is applied to the second select transistor during the second read operation.
23. The memory device according to claim 22 , wherein the memory device receives the address after receiving a first command, and the memory device executes the first read operation for the address after receiving a second command.
24. The memory device according to claim 23 , wherein the memory device is configured to output a busy signal after receiving the first command, the address, and the second command.
25. The memory device according to claim 24 , wherein the memory device executes the second read operation for an address which is different from the address received after the first command responsive to the memory device receiving a third command.
26. The memory device according to claim 25 , wherein the memory device outputs data of the first read operation and a ready signal after receiving the third command.
27. The memory device according to claim 26 , wherein the memory device outputs a busy signal responsive to the memory device receiving the third command again.
28. The memory device according to claim 27 , wherein the memory device discharges the first or second voltages responsive to the memory device receiving a fourth command while outputting the ready signal.