Methods and systems of a memory controller for hierarchical immutable content-addressable memory processor
Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.
1. A memory controller comprising:
a fetcher to:
receive a data element to be written to a physical memory having a plurality of physical memory blocks, wherein each physical memory block is associated with an indication of whether it is active, and is further structured to include a reference count field indicating a number of references to the physical memory block, and a data field; and
determine whether the data element is already contained in an active physical memory block of the physical memory; and
a block data directory to allocate a physical memory block of the physical memory using the reference count field of the physical memory block, responsive to a determination by the fetcher that the data element is not already contained in any active physical memory block of the physical memory.
2. The memory controller of claim 1 , wherein the fetcher is to receive the data element with a block fetch by content (BFBC) instruction.
3. The memory controller of claim 2 , wherein the fetcher is to return a block address corresponding to the active physical memory block that already contains the data element responsive to reception of the BFBC instruction and responsive to a determination by the fetcher that the data element is already contained in the active physical memory block.
4. The memory controller of claim 3 , wherein the block address is a virtual block identifier (ID).
5. The memory controller of claim 3 , wherein the block address is a physical block identifier (ID).
6. The memory controller of claim 2 , wherein the fetcher is to return a block address corresponding to the block allocated by the block data directory responsive to reception of the BFBC instruction and responsive to a determination by the fetcher that the data element is not already contained in any of the active physical memory blocks.
7. The memory controller of claim 1 , further comprising a virtual to physical block ID mapping (VPBIM) to map virtual block identifiers (IDs) to physical block IDs for one or more contents of the physical memory.
8. The memory controller of claim 1 , wherein the physical memory is a binary content-addressable memory (CAM) and each physical memory block has a fixed storage capacity.
9. A method of computer memory management at a memory controller comprising:
receiving a data element to be written to a physical memory having a plurality of physical memory blocks, wherein each physical memory block is associated with an indication of whether it is active, and is further structured to include a reference count field indicating a number of references to the physical memory block, and a data field;
determining whether the data element is contained in any active physical memory block as an existing data element; and
using the existing data element in response to a determination that one of the active physical memory blocks already contains the data element as the existing data element.
10. The method of claim 9 , further comprising:
returning a block address corresponding to the active physical memory block that contains the existing data element in response to receiving the data element.
11. The method of claim 10 , wherein the block address is a virtual block identifier (ID).
12. The method of claim 10 , wherein the block address is a physical block identifier (ID).
13. The method of claim 9 , wherein the data element is a first data element, the existing data element is a first existing data element, and the method further comprises:
receiving a second data element to be written to the physical memory;
determining whether the second data element is contained in any active physical memory block as a second existing data element; and
allocating a physical memory block using the reference count field of the physical memory block, in response to determining that the second data element is not contained in any of the active physical memory blocks as a second existing data element.
14. The method of claim 13 , further comprising:
returning a physical block identifier (ID) of the allocated physical memory block in response to receiving the second data element.
15. A computer system comprising:
a memory comprising a plurality of physical memory blocks, wherein each physical memory block is associated with an indication of whether it is active, and is further structured to include a reference count field indicating a number of references to the physical memory block, and a data field; and
a memory controller coupled with the memory to:
receive a data element to be written to the memory;
determine whether the data element is already contained in any active physical memory block of the memory as an existing data element;
use the existing data element in response to a determination that the data element is already contained in one of the active physical memory blocks as the existing data element; and
allocate a physical memory block of the plurality of physical memory blocks using the reference count field of the physical memory block, in response to a determination that the data element is not already contained in any active physical memory block of the plurality of physical memory blocks.
16. The computer system of claim 15 , wherein the memory is a content-addressable physical memory.
17. The computer system of claim 15 , wherein the memory is conventional dynamic random access memory (DRAM).
18. The computer system of claim 15 , further comprising a processor coupled with the memory controller, wherein the memory controller is to receive the data element from the processor.
19. The computer system of claim 18 , wherein the data element is included in a block fetch by content (BFBC) instruction.
20. The computer system of claim 18 , wherein the memory is a content-addressable physical memory and the processor includes a content-addressable cache.