Programmable logic device with integrated high voltage power FET
A programmable logic device (PLD) includes a programmable fabric, a plurality of input/output (I/O) blocks, and a plurality of high voltage power field effect transistors (FETs). The PLD can be programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric. Each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.
1. A programmable logic device (PLD) comprising:
a programmable fabric including a plurality of logic elements and a plurality of routing channels;
a plurality of input/output (I/O) blocks; and
a plurality of high voltage power transistors,
wherein the PLD is programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric,
wherein each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD, and
wherein a first high voltage power transistor of the plurality of high voltage power transistors is programmed to provide a power supply, and wherein operating characteristics of the power supply is programmed by the programming the programmable fabric.
2. The PLD of claim 1 , wherein the plurality of logic elements includes one or more of memory blocks including a static random-access memory (SRAM), and a non-volatile memory, look up tables, flip flops, and logic gates.
3. The PLD of claim 1 , wherein each of the plurality of high voltage power transistors is capable of handling a voltage ranging from 12V to 80V and current up to 12 A.
4. The PLD of claim 1 , wherein the drain pad and the source pad are connected to an external electric element or device.
5. The PLD of claim 1 , wherein the operating characteristics of the power supply include voltage levels, turn-on and turn-off sequences, a switching frequency, a voltage ramp rate, tracking between outputs, protection and monitoring.
6. The PLD of claim 1 , wherein a first group of the plurality of high voltage power transistors is coupled to provide a first power switch.
7. The PLD of claim 6 , wherein the first power switch is one of a voltage mode buck switching converter, a current mode buck switching converter, a boost regulator, a buck-boost regulator, a low drop-out (LDO) regulator, a load switch, a mux, a battery charger, an external switching controller, a gate driver, and an integrator.
8. The PLD of claim 6 , wherein a second group of the plurality of high voltage power transistors is coupled to provide a second power switch, and wherein the first power switch is a first buck converter, and the second power switch is a second buck converter.
9. The PLD of claim 1 , wherein the plurality of high voltage power transistors includes a DMOS high voltage power FET integrated to a CMOS circuit.
10. A PLD comprising:
a programmable fabric including a plurality of logic elements and a plurality of routing channels;
a plurality of input/output (I/O) blocks; and
a plurality of high voltage power transistors,
wherein the PLD is programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric,
wherein each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD, and
wherein a second high voltage power transistor of the plurality of high voltage power transistors is programmed to drive an external high voltage power FET.
11. A PLD comprising:
a programmable fabric including a plurality of logic elements and a plurality of routing channels;
a plurality of input/output (I/O) blocks;
a plurality of high voltage power transistors; and
a plurality of functional blocks including adaptive blocks,
wherein the PLD is programmed to connect one or more of the plurality of I/O blocks, one or more of the plurality of high voltage power transistors via the programmable fabric, and
wherein each of the plurality of high voltage power transistors includes a drain pad and a source pad that are exposed via external pins of the PLD.
12. The PLD of claim 11 , wherein the adaptive blocks comprise one or more of an analog-to-digital converter (ADC) block, a comparator block, a memory block, a pulse-width modulation (PWM) block, a voltage reference block, and a timer block.