IP Library Granted Patent US 9,768,158
Granted Patent B2
US 9,768,158 · App. 15/337,234 · Granted Sep 19, 2017

Static electricity protection circuit, electro-optic device and electronic device

Inventors: Hidenori Sokabe (Chitose, JP); Masahito Yoshii (Chitose, JP)
Assignee: Seiko Epson Corporation
H01L27/0266H01L27/1203H01L27/1244
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,768,158
App. No.
15/337,234
Granted
Sep 19, 2017
Kind
B2
Abstract

In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.

Claims (24)

1. An electro-optic device comprising:

a scanning line;

a data line;

a pixel;

a scanning line driving circuit; and

a static electricity protection circuit,

wherein the static electricity protection circuit includes

a first p-type transistor;

a first n-type transistor;

a second p-type transistor;

a second n-type transistor;

a first wiring line that supplies a first electric potential;

a second wiring line connected to the scanning line driving circuit; and

a third wiring line that supplies a second electric potential higher than the first electric potential,

wherein

the first p-type transistor is disposed between the first wiring line and the second wiring line, and a gate of the first p-type transistor and one of a source and a drain of the first p-type transistor are connected to the second wiring line,

the first n-type transistor is disposed between the first wiring line and the second wiring line, and a gate of the first n-type transistor and one of a source and a drain of the first n-type transistor are connected to the first wiring line,

the second p-type transistor is disposed between the third wiring line and the second wiring line, a gate of the second p-type transistor and one of a source and a drain of the second p-type transistor are connected, and the other one of the source and the drain of the second p-type transistor is connected to the second wiring line, and

the second n-type transistor is disposed between the third wiring line and the second wiring line, a gate of the second n-type transistor and one of a source and a drain of the second n-type transistor are connected, and the other one of the source and the drain of the second n-type transistor is connected to the third wiring line.

2. An electronic device comprising the electro-optic device according to claim 1 .

3. The electro-optic device according to claim 1 ,

wherein an on-state electric current of the first p-type transistor is the same as a current of the second p-type transistor.

4. The electro-optic device according to claim 1 ,

wherein an on-state electric current of the first n-type transistor is the same as a current of the second n-type transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050197/0212 →
Priority Claims (1)
JP 2013-137856 · Jul 1, 2013 · national
Continuity (2)
Continuation 14314808 · Jun 25, 2014
Related Publication 20170047318A1 · Feb 16, 2017