Power semiconductor device

1. A power semiconductor device comprising:

a substrate;

an anode electrode;

a cathode electrode;

a well region disposed inside the substrate below the anode electrode, and having a p-type conductivity;

an NISO region disposed below the well region, and having a first n-type impurity concentration, inside the substrate; and

an n-type buried layer disposed below the NISO region and having a second n-type impurity concentration greater than the first n-type impurity concentration, inside the substrate,

the n-type buried layer being below substantially an entirety of the NISO region.

2. The power semiconductor device of claim 1 , wherein the well region and the NISO region define a p-n junction diode.

3. The power semiconductor device of claim 1 , wherein at least a portion of a bottom surface of the NISO region is in contact with an upper surface of the n-type buried layer.

4. A power semiconductor device, comprising:

a substrate;

an anode electrode;

a cathode electrode;

a well region disposed inside the substrate below the anode electrode, and having p-type conductivity;

an NISO region disposed below the well region, and having a first n-type impurity concentration, inside the substrate;

an n-type buried layer disposed below the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration; and

an n-type barrier layer disposed on a side of the NISO region, inside the substrate.

5. The power semiconductor device of claim 4 , wherein the n-type barrier layer is disposed on the n-type buried layer.

6. The power semiconductor device of claim 4 , wherein at least a portion of a bottom surface of the n-type barrier layer is in contact with an upper surface of the n-type buried layer.

7. The power semiconductor device of claim 4 , wherein the n-type barrier layer has a third n-type impurity concentration greater than the first n-type impurity concentration.

8. The power semiconductor device of claim 4 , further comprising an n-type sink disposed on the n-type barrier layer, inside the substrate,

the n-type sink having a third n-type impurity concentration greater than the first n-type impurity concentration.

9. The power semiconductor device of claim 4 , further comprising an element isolation region disposed on one side of the NISO region, inside the substrate,

the element isolation region including an upper element isolation layer and a lower element isolation layer disposed below the upper element isolation layer.

10. The power semiconductor device of claim 9 , wherein a bottom surface of the lower element isolation layer is located at a higher level than a bottom surface of the n-type buried layer.

11. A power semiconductor device, comprising:

a base substrate;

a first semiconductor layer disposed on the base substrate;

a second semiconductor layer disposed on the first semiconductor layer;

an anode electrode and a cathode electrode disposed on the second semiconductor layer;

a p-type well region disposed below the anode electrode inside the second semiconductor layer;

an NISO region disposed below the p-type well, and in which at least a portion is located inside the first semiconductor layer;

an n-type buried layer disposed below the NISO region, and in which at least a portion is located inside the base substrate; and

an element isolation region disposed on a side of the NISO region, the element isolation region including:

a lower element isolation layer having at least a portion located inside the first semiconductor layer, and

an upper element isolation layer having at least a portion located inside the second semiconductor layer and on the lower element isolation layer.

12. The power semiconductor device of claim 11 , wherein the NISO region has a first n-type impurity concentration, and the n-type buried layer has a second n-type impurity concentration greater than the first n-type impurity concentration.

13. The power semiconductor device of claim 11 , further comprising an n-type barrier layer disposed on one side of the NISO region and disposed on the n-type buried layer.

14. The power semiconductor device of claim 13 , wherein the NISO region has a first n-type impurity concentration, and the n-type barrier layer has a second n-type impurity concentration greater than the first n-type impurity concentration.

15. A power semiconductor device comprising:

a substrate; and

a plurality of unit cells disposed on the substrate, each of the plurality of unit cells including:

an anode electrode and a cathode electrode disposed at a distance away from each other on the substrate,

a well region disposed inside the substrate below the anode electrode, and having p-type conductivity; and

an NISO region disposed below the well region, and having a first n-type impurity concentration inside the substrate; and

an n-type buried layer disposed below the NISO region of each of the plurality of unit cells and having a second n-type impurity concentration greater than the first n-type impurity concentration inside the substrate,

the n-type buried layer overlapping with substantially an entire area of the plurality of unit cells.

16. The power semiconductor device of claim 15 , wherein the cathode electrode inside one unit cell among the plurality of unit cells is connected to the cathode electrode inside a unit cell adjacent thereto.

17. The power semiconductor device of claim 15 , wherein each of the plurality of unit cells further includes an n-type barrier layer disposed on both sides of the NISO region.

18. The power semiconductor device of claim 4 , wherein at least a portion of a bottom surface of the NISO region is in contact with an upper surface of the n-type buried layer.

19. The power semiconductor device of claim 4 , wherein the n-type buried layer is below substantially an entirety of the NISO region.

20. The power semiconductor device of claim 4 , further comprising an n-type barrier layer disposed on a side of the NISO region.