Voltage controlled oscillator with common mode adjustment start-up
The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.
1. An apparatus comprising:
a voltage controlled oscillator (VCO) having an LC tank and at least one pair of transistors cross-coupled across a pair of common nodes of the LC tank, with a drain of one transistor of the pair and a gate of the other transistor of the pair connected to one of the pair of common nodes of the LC tank, and a gate of the one transistor of the pair and a drain of the other transistor of the pair connected to the other of the pair of common nodes of the LC tank;
a power supply system comprising a voltage supply coupled to a low-dropout (LDO) voltage regulator;
a control circuit coupled to monitor the pair of common nodes, the control circuit comprising:
a sequencer coupled to the LDO voltage regulator to control the LDO voltage regulator to:
provide a first supply voltage to the VCO such that a voltage difference between a common mode voltage at the pair of common nodes and a source voltage of transistors of the pair of transistors is less than a threshold voltage of the transistors of the pair of transistors;
provide a second supply voltage higher than the first supply voltage to the VCO to temporarily adjust the common mode voltage to increase the voltage difference and initiate differential oscillation in the VCO at the common nodes, the second supply voltage being provided until the control circuit determines steady-state oscillation is established; and
provide the first supply voltage to the VCO once the control circuit determines steady-state oscillation is established thereby reducing power consumption while sustaining the oscillation.
2. An apparatus according to claim 1 , wherein the control circuit further comprises a process monitor coupled to detect process and voltage conditions at the common nodes of the VCO, the process monitor also coupled to the sequencer.
3. An apparatus according to claim 2 , wherein the VCO comprises two complementary pairs of cross-coupled transistors, with one of the complementary pairs comprising a pair of NMOS transistors and the other of the complementary pairs comprising a pair of PMOS transistors, wherein the control circuit is configured to:
increase the common mode voltage independently of the LDO voltage regulator in response to the detected process and voltage conditions indicating that the voltage difference is less than a transistor threshold voltage of the pair of NMOS transistors; and
decrease the common mode voltage independently of the LDO voltage regulator in response to the detected process and voltage conditions indicating that the voltage difference is less than a transistor threshold voltage of the pair of PMOS transistors.
4. An apparatus according to claim 3 , wherein the control circuit further comprises:
a pair of pull-up transistors coupled between the pair of common nodes and a pull-up supply voltage higher than the first supply voltage; and
a pair of pull-down transistors coupled between the pair of common nodes and one of ground and a negative supply voltage,
wherein the control circuit is further configured to selectively:
increase the common mode voltage by selectively activating the pair of pull-up transistors; and
decrease the common mode voltage by selectively activating the pair of pull-down transistors.
5. An apparatus according to claim 2 , wherein the process monitor comprises at least one ring oscillator on an integrated circuit chip common to the VCO, and where the at least one ring oscillator is made of the same type of PMOS and NMOS transistors as in the VCO.
6. An apparatus according to claim 1 , wherein the VCO comprises a single pair of NMOS transistors cross-coupled across the common nodes, wherein the first supply voltage is provided by the LDO voltage regulator to a center tap of an inductor of the LC tank, and wherein the control circuit comprises a pair of pull-up transistors coupled between the pair of common nodes and a pull-up supply voltage higher than the first supply voltage.
7. An apparatus according to claim 1 , wherein the VCO comprises a single pair of PMOS transistors cross-coupled across the common nodes, wherein the first supply voltage is provided by the LDO voltage regulator to the PMOS transistors, and a center tap of an inductor of the LC tank is grounded while powering the VCO during steady-state oscillation, and wherein the control circuit comprises a pair of pull-down transistors coupled between the pair of common nodes and a negative supply voltage.
8. An apparatus according to claim 1 , wherein the control circuit is configured to monitor oscillations at the pair of common nodes during steady-state oscillation and adjust the common mode voltage to improve matching of rising and falling transitions of signals at the pair of common nodes.
9. An apparatus according to claim 1 , wherein the control circuit is configured to adjust the common mode voltage for a predetermined time period and to a predetermined voltage level when temporarily adjusting the common mode voltage.
10. An apparatus according to claim 1 , wherein the control circuit is configured to monitor the pair of common nodes, and adjust the common mode voltage and retain the adjusted common mode voltage until steady-state oscillation is detected.
11. A method of controlling a voltage controlled oscillator (VCO) having an LC tank and at least one pair of transistors cross-coupled across a pair of common nodes of the LC tank, with a drain of one transistor of the pair and a gate of the other transistor of the pair connected to one of the pair of common nodes of the LC tank, and a gate of the one transistor of the pair and a drain of the other transistor of the pair connected to the other of the pair of common nodes of the LC tank, the method comprising:
monitoring the pair of common nodes with a control circuit;
controlling a low-dropout (LDO) voltage regulator with a sequencer, the controlling comprising:
providing a first supply voltage to the VCO such that a voltage difference between a common mode voltage at the pair of common nodes and a source voltage of transistors of the pair of transistors is less than a threshold voltage of the transistors of the pair of transistors;
providing a second supply voltage higher than the first supply voltage to the VCO to temporarily adjust the common mode voltage to increase the voltage difference and initiate differential oscillation in the VCO at the common nodes, the second supply voltage being provided until the control circuit determines steady-state oscillation is established; and
providing the first supply voltage to the VCO once the control circuit determines steady-state oscillation is established thereby reducing power consumption while sustaining the oscillation.
12. A method according to claim 11 , further comprising detecting process and voltage conditions at the common nodes of the VCO with a process monitor.
13. A method according to claim 12 , wherein the VCO comprises two complementary pairs of cross-coupled transistors, with one of the complementary pairs comprising a pair of NMOS transistors and the other of the complementary pairs comprising a pair of PMOS transistors, wherein the method further comprises:
increasing the common mode voltage independently of the LDO voltage regulator in response to the detected process and voltage conditions indicating that the voltage difference is less than a transistor threshold voltage of the pair of NMOS transistors; and
decreasing the common mode voltage independently of the LDO voltage regulator in response to the detected process and voltage conditions indicating that the voltage difference is less than a transistor threshold voltage of the pair of PMOS transistors.
14. A method according to claim 13 , wherein the control circuit comprises:
a pair of pull-up transistors coupled between the pair of common nodes and a pull-up supply voltage higher than the first supply voltage; and
a pair of pull-down transistors coupled between the pair of common nodes and one of ground and a negative supply voltage,
wherein the method further comprises selectively:
increasing the common mode voltage by selectively activating the pair of pull-up transistors; and
decreasing the common mode voltage by selectively activating the pair of pull-down transistors.
15. A method according to claim 12 , wherein the process monitor comprises at least one ring oscillator on an integrated circuit chip common to the VCO, and where the at least one ring oscillator is made of the same type of PMOS and NMOS transistors as in the VCO.
16. A method according to claim 11 , wherein the VCO comprises a single pair of NMOS transistors cross-coupled across the common nodes, wherein the method further comprises providing the first supply voltage by the LDO voltage regulator to a center tap of an inductor of the LC tank, and wherein the control circuit comprises a pair of pull-up transistors coupled between the pair of common nodes and a pull-up supply voltage higher than the first supply voltage.
17. A method according to claim 11 , wherein the VCO comprises a single pair of PMOS transistors cross-coupled across the common nodes, wherein the method further comprises providing the first supply voltage by the LDO voltage regulator to the PMOS transistors, and a center tap of an inductor of the LC tank is grounded while powering the VCO during steady-state oscillation, and wherein the control circuit comprises a pair of pull-down transistors coupled between the pair of common nodes and a negative supply voltage.
18. A method according to claim 11 , further comprising monitoring oscillations at the pair of common nodes during steady-state oscillation and adjusting the common mode voltage to improve matching of rising and falling transitions of signals at the pair of common nodes.
19. A method according to claim 11 , further comprising adjusting the common mode voltage for a predetermined time period and to a predetermined voltage level when temporarily adjusting the common mode voltage.
20. A method according to claim 11 , further comprising monitoring the pair of common nodes, and adjusting the common mode voltage and retaining the adjusted common mode voltage until steady-state oscillation is detected.