Memory controller, memory system, and memory control method

1. A memory system comprising:

a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, each of the memory areas being a unit for writing of data; and

a controller circuit configured to write data into the nonvolatile memory in a first method and a second method, the controller circuit including an error correction code encoder configured to encode data to generate a parity, wherein,

in the first method,

the controller circuit is configured to:

acquire N pieces of first user data, N being a natural number; and

encode, using the error correction code encoder, the N pieces of first user data respectively to generate N first parities; and

write the N pieces of first user data and the N first parities into a first memory area among the plurality of memory areas,

in the second method,

the controller circuit is configured to:

acquire M pieces of second user data, M being a natural number larger than N, a size of each of the second user data being smaller than that of each of the first user data;

encode, using the error correction code encoder, the M pieces of second user data respectively to generate M second parities, a size of each of the M second parities being the same as that of each of the N first parities;

write the M pieces of second user data and the M second parities into a second memory area among the plurality of memory areas,

wherein a number of correctable bits in each of the M pieces of second user data using the second parity is larger than a number of correctable bits in each of the N pieces of first user data using the first parity,

the controller circuit further includes a write counter configured to count a number of times of writing of data on each of the plurality of memory areas,

in a case where the number of times of writing of data on a memory area among the plurality of memory areas is smaller than or equal to a first threshold, the controller circuit uses the first method to write data into the memory area, and

in a case where the number of times of writing of data on the memory area is larger than the first threshold, the controller circuit uses the second method to write data into the memory area.

2. The memory system according to claim 1 , the controller circuit further including an erase counter configured to count a number of times of erasing of data from each of the plurality of memory areas, wherein,

in a case where the number of times of erasing of data from a memory area among the plurality of memory areas is smaller than or equal to a first threshold, the controller circuit uses the first method to write data into the memory area, and

in a case where the number of times of erasing of data from the memory area is larger than the first threshold, the controller circuit uses the second method to write data into the memory area.

3. The memory system according to claim 2 , wherein,

in a case where a total size of parities to be stored in the nonvolatile memory is less than a second threshold, the controller circuit uses the second method.

4. The memory system according to claim 1 , the controller circuit further including an error correction code decoder configured to decode data and a parity to detect an error bit in the data, wherein,

in a case where a rate of error bits detected in third user data stored in a memory area among the plurality of memory areas is smaller than or equal to a first threshold, the controller circuit uses the first method to write data into the memory area, and

in a case where a rate of error bits detected in fourth user data stored in the memory area is larger than the first threshold, the controller circuit uses the second method to write data into the memory area.

5. The memory system according to claim 4 , wherein,

in a case where a total size of parities to be stored in the nonvolatile memory is less than a second threshold, the controller circuit uses the second method.

6. The memory system according to claim 1 , wherein,

in a case where a total size of parities to be stored in the nonvolatile memory is less than a first threshold, the controller circuit uses the second method.

7. The memory system according to claim 6 , wherein,

the controller circuit is configured to determine the first threshold so that a write performance of the memory system satisfies a predetermined performance.

8. The memory system according to claim 1 , wherein,

in a case where a total size of parities to be stored in the nonvolatile memory is less than a second threshold, the controller circuit uses the second method.

9. The memory system according to claim 1 , wherein,

the parity generated for data is capable of at least one of detecting of an error bit in the data and correcting of an error bit in the data.

10. The memory system according to claim 1 , wherein, each of the plurality of memory areas comprises a page.

11. The memory system according to claim 1 , wherein

a total size of the N pieces of first user data and the N first parities is equal to a total size of the M pieces of second user data and the M second parities.

12. The memory system according to claim 1 , wherein,

a total size of the M pieces of second user data written into the second memory area in the second method is smaller than a total size of the N pieces of first user data written into the first memory area in the first method.

13. The memory system according to claim 1 , wherein,

the controller circuit is further configured to convert a logical address of user data designated by a host into a physical address of the nonvolatile memory in which the user data is stored, and

each piece of the first user data is a minimum unit for the address conversion, and a sum of a plurality pieces of the second user data is the minimum unit for the address conversion.

14. A method of writing data into a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, each of the memory areas being a unit for writing of data, said method comprising:

in a first method,

acquiring N pieces of first user data, N being a natural number;

encoding the N pieces of first user data respectively to generate N first parities; and

writing the N pieces of first user data and the N first parities into a first memory area among the plurality of memory areas,

in a second method,

acquiring M pieces of second user data, M being a natural number larger than N, a size of each of the second user data being smaller than that of each of the first user data;

encoding the M pieces of second user data respectively to generate M second parities, a size of each of the M second parities being the same as that of each of the N first parities; and

writing the M pieces of second user data and the M second parities into a second memory area among the plurality of memory areas,

wherein a number of correctable bits in each of the M pieces of second user data using the second parity is larger than a number of correctable bits in each of the N pieces of first user data using the first parity and the method further includes

counting a number of times of writing of data on each of the plurality of memory areas,

in a case where the number of times of writing of data on a memory area among the plurality of memory areas is smaller than or equal to a first threshold, using the first method to write data into the memory area, and

in a case where the number of times of writing of data on the memory area is larger than the first threshold, using second method to write data into the memory area.

15. The method according to claim 14 , wherein

a total size of the N pieces of first user data and the N first parities is equal to a total size of the M pieces of second user data and the M second parities.

16. The method according to claim 14 , wherein,

a total size of the M pieces of second user data written into the second memory area in the second method is smaller than a total size of the N pieces of first user data written into the first memory area in the first method.

17. The method according to claim 14 , wherein,

in a case where a total size of parities to be stored in the nonvolatile memory is less than a first threshold, the second method is used.

18. A memory system comprising:

a nonvolatile memory that includes a plurality of memory areas, each of the memory areas being a unit for writing of data; and

a controller circuit configured to write data into the nonvolatile memory in a first method and a second method, the controller circuit including an error correction code encoder configured to encode data to generate a parity, wherein,

in the first method, the controller circuit is configured to:

encode, using the error correction code encoder, N data clusters respectively to generate N first parities, N being a natural number larger than one; and

write the N data clusters and the N first parities into a first memory area among the plurality of memory areas,

in the second method, the controller circuit is configured to:

divide M data clusters respectively into two sub data clusters to generate 2M sub data clusters, M being a natural number smaller than N, a size of each of the sub data clusters being smaller than that of each of the data clusters;

encode, using the error correction code encoder, each of the 2M sub data clusters to generate 2M second parities, a size of each of the 2M second parities being the same as that of each of the N first parities; and

write the 2M sub data clusters and the 2M second parities into a second memory area among the plurality of memory areas,

wherein a number of correctable bits in the sub data cluster using the second parity is larger than a number of correctable bits in each of the data clusters using the first parity,

the controller circuit further includes a write counter configured to count a number of times of writing of data on each of the plurality of memory areas,

in a case where the number of times of writing of data on a memory area among the plurality of memory areas is smaller than or equal to a first threshold, the controller circuit uses the first method to write data into the memory area, and

in a case where the number of times of writing of data on the memory area is larger than the first threshold, the controller circuit uses the second method to write data into the memory area.

19. The memory system according to claim 18 , wherein

a total size of the N data clusters and the N first parities is equal to a total size of the M data clusters and the 2M second parities.

20. A memory system comprising:

a nonvolatile memory that includes a plurality of memory areas including a first memory area and a second memory area, each of the memory areas being a unit for writing of data; and

a controller circuit configured to write data into the nonvolatile memory in a first method and a second method, the controller circuit including an error correction code encoder configured to encode data to generate parity data, wherein,

in the first method, the controller circuit is configured to

write, in a first memory area, first data and N pieces of first parity data, N being a natural number, the first data including N pieces of second data, each of the N pieces of second data having a second size, each of the N pieces of first parity data being generated by encoding each of N pieces of second data and having a first size,

in the second method, the controller circuit is configured to

write, in a second memory area having the same size as the first memory area, third data and M pieces of second parity data, M being a natural number, the third data including M pieces of fourth data, a size of the third data being smaller than a size of the first data, each of the M pieces of second parity data being generated by encoding each of M pieces of fourth data and having the first size, a size of each of M pieces of fourth data being smaller than a size of each of N pieces of second data,

wherein a number of correctable bits in each of the fourth data using the second parity data is larger than a number of correctable bits in each of the third data using the first parity data,

the controller circuit further includes a write counter configured to count a number of times of writing of data on each of the plurality of memory areas,

in a case where the number of times of writing of data on a memory area among the plurality of memory areas is smaller than or equal to a first threshold, the controller circuit uses the first method to write data into the memory area, and

in a case where the number of times of writing of data on the memory area is larger than the first threshold, the controller circuit uses the second method to write data into the memory area.

21. The memory system according to claim 20 , wherein M is larger than N.