Cascode semiconductor package and related methods
A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically coupled with the base. A depletion mode gallium nitride field-effect transistor (GaN FET) and an enhancement mode laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS FET) are also coupled with the base. The gate connector and a gate contact of the LDMOS FET are both included in a first electrical node, the source connector and a source contact of the LDMOS FET are both included in a second electrical node, and the drain connector and a drain contact of the GaN FET are both included in a third electrical node. The GaN FET and LDMOS FET together form a cascode that operates as an enhancement mode amplifier. The semiconductor package does not include an interposer between the GaN FET and the base or between the LDMOS FET and the base.
1. A semiconductor package, comprising:
an electrically conductive base (base) comprising a source connector;
a drain connector electrically coupled with the base;
a gate connector electrically coupled with the base;
a gallium nitride field-effect transistor (GaN FET) coupled with the base, wherein the semiconductor package does not comprise an interposer between the GaN FET and the base, and;
a semiconductor field-effect transistor (FET) coupled with the base and electrically coupled with the GaN FET, the GaN FET and the FET together forming a cascode.
2. The semiconductor package of claim 1 , wherein the gate connector and a gate contact of the FET are both comprised in a first electrical node, the source connector and a source contact of the FET are both comprised in a second electrical node, and the drain connector and a drain contact of the GaN FET are both comprised in a third electrical node.
3. The semiconductor package of claim 1 , wherein the GaN FET is a planar GaN FET comprising a source contact, a gate contact, and a drain contact on a first side of the GaN FET.
4. The semiconductor package of claim 1 , wherein the GaN FET and the FET are within a perimeter of the base.
5. The semiconductor package of claim 1 , wherein the GaN FET is a depletion mode GaN FET.
6. The semiconductor package of claim 1 , wherein the FET is an enhancement mode FET.
7. The semiconductor package of claim 1 , wherein the GaN FET is a high electron mobility transistor (HEMT).
8. The semiconductor package of claim 1 , wherein the cascode operates as an enhancement mode amplifier.
9. The semiconductor package of claim 1 , wherein the FET is configured as a source-down FET.
10. A semiconductor package, comprising:
a cascode comprising:
a gallium nitride field-effect transistor (GaN FET) electrically coupled with a semiconductor field-effect transistor (FET);
wherein the semiconductor package does not comprise an interposer coupled between the GaN FET and a base of the semiconductor package or the FET and the base of the semiconductor package;
wherein a source of the FET and a gate of the GaN FET are both electrically coupled with a source of the semiconductor package;
wherein a gate of the FET is electrically coupled with a gate of the semiconductor package, and;
wherein a drain of the GaN FET is electrically coupled with a drain of the semiconductor package.
11. The semiconductor package of claim 10 , further comprising an encapsulant encapsulating the GaN FET and the FET and exposing the gate, the source, and the drain of the semiconductor package through the encapsulant.
12. The semiconductor package of claim 10 , wherein the GaN FET is a depletion mode GaN FET.
13. The semiconductor package of claim 10 , wherein the FET is an enhancement mode FET.
14. The semiconductor package of claim 10 , wherein the GaN FET is a high electron mobility transistor (HEMT).
15. The semiconductor package of claim 10 , wherein the cascode operates as an enhancement mode amplifier.
16. The semiconductor package of claim 10 , wherein the FET comprises a first side comprising the source of the FET and a second side comprising the gate of the FET and a drain of the FET.
17. The semiconductor package of claim 10 , wherein the GaN FET comprises a first side coupled with a base of the semiconductor package and a second side comprising the gate of the GaN FET, the drain of the GaN FET and a source of the GaN FET.
18. The semiconductor package of claim 10 , wherein the FET is configured as a source-down FET.
19. A semiconductor package, comprising:
a depletion-mode gallium nitride high electron mobility transistor (GaN HEMT) comprising a first side physically coupled with an electrically conductive base (base) and a second side comprising a source contact, a drain contact, and a gate contact, the gate contact electrically coupled with the base through an electrical coupler;
a source-down semiconductor field-effect transistor (FET) comprising a first side comprising a source contact physically and electrically coupled with the base and a second side comprising a gate contact and a drain contact;
wherein the GaN HEMT and the FET are electrically coupled together to form an enhancement mode cascode;
wherein the base comprises a source connector and wherein the semiconductor package further comprises a gate connector and a drain connector, the gate connector electrically coupled with the gate contact of the FET and the drain connector electrically coupled with the drain contact of the GaN HEMT;
wherein an encapsulant encapsulates the GaN HEMT and the FET and at least partially encapsulates the source connector, the gate connector and the drain connector, and;
wherein a gate contact of the gate connector, a source contact of the source connector, and a drain contact of the drain connector are exposed through openings in the encapsulant.