Socket structure for three-dimensional memory
Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.
1. A method for forming a staircase contact socket region, comprising:
providing a stack that includes a plurality of planar electrodes and a plurality of insulating layers, wherein adjacent planar electrodes are separated from one another by an insulating layer;
placing a mask on the stack;
etching a first portion of a first insulating layer included in the plurality of insulating layers not under the mask to expose a first portion of a first planar electrode included in the plurality of planar electrodes;
pulling back the mask;
after pulling back the mask, etching a second portion of the first insulating layer exposed by pulling back the mask, etching a part of the first portion of the first planar electrode and etching a first portion of a second insulating layer included in the plurality of insulating layers, wherein an edge of the second insulating layer formed by the etching is sloped and extends from an edge of the first planar electrode to between the edge of the first planar electrode and an edge of a second planar electrode included in the plurality of planar electrodes.
2. The method of claim 1 , wherein an edge of the first insulating layer is sloped.
3. The method of claim 2 , wherein the edges of the first and second planar electrodes are vertical.
4. The method of claim 3 , further comprising:
forming a plurality of connecting conductors, wherein each connecting conductor is electrically connected to a top surface and an edge surface of one of the planar electrodes.