Media streaming synchronization
A system and method for closely synchronizing the transmission of real-time data streams is described. Synchronization data is transmitted by a cycle master for receipt by one or more cycle slaves. A cycle slave updates an internal state based on synchronization data received from the cycle master. This internal state may govern reproduction of received real-time data streams by the cycle slave. Such synchronization data may be inserted into transmitted media streams. The cycle slave internal state may be more accurately set by calculating timing differences between the cycle master and cycle slave and periodically adjusting that internal state between receipt of the synchronization data from the cycle master.
1. A method of synchronizing the transmission of real-time data streams from a master device to a slave device, the method comprising:
receiving, by a slave device, a stream of media packets and a synchronization packet inserted into the stream of media packets, the synchronization packet comprising synchronization data from a master device, wherein the synchronization packet is distinct from the media packets;
updating an internal state of the slave device based on the synchronization data; and
gating a real-time data stream from the master device based on the updated internal state.
2. The method of claim 1 , wherein the internal state controls reproduction of the real-time data streams in the slave device.
3. The method of claim 1 , wherein the synchronization data is inserted into the real-time data streams.
4. The method of claim 1 , wherein updating the internal state of the slave device based on the synchronization data comprises:
calculating timing differences between the master device and the slave device; and
periodically adjusting the internal state between receipt of sequential synchronization data from the master device.
5. The method of claim 1 , wherein a rate of updating the internal state is variable.
6. A method of synchronizing a first clock in a first device and a second clock in a second device using a wireless network, the method comprising:
sending a synchronization packet over the wireless network, the synchronization packet including a frame body that comprises synchronization information; and
performing a synchronization based on the synchronization packet, wherein the synchronization ensures a timing error of less than 4 μs between the first and second devices, wherein sending the synchronization packet includes:
generating the synchronization packet using a first timestamp associated with the first device; and
inserting the synchronization packet between data packets.
7. The method of claim 6 , wherein the first timestamp in the first device is generated by a first oscillator coupled to a first timestamp timer.
8. The method of claim 6 , wherein a rate of sending the synchronization packet can be varied based on a feedback signal from the second device.
9. A method of synchronizing a first clock in a first device and a second clock in a second device using a wireless network, the method comprising:
receiving a synchronization packet over the wireless network; and
performing a synchronization based on the synchronization packet, wherein the synchronization ensures a timing error of less than 4 μs between the first and second devices,
wherein receiving the synchronization packet includes:
receiving packets over the wireless network;
distinguishing between a non-synchronization packet and the synchronization packet;
extracting a first timestamp associated with the first device from the synchronization packet;
detecting a timing reference point event in the second device; and
initializing a timestamp delta counter based on the timing reference point event.
10. The method of claim 9 , wherein receiving the synchronization packet further includes updating a second timestamp stored in a second timestamp timer based on a value in the timestamp delta counter and the first timestamp.
11. The method of claim 10 , wherein the second timestamp timer and the timestamp delta counter are incremented by a second oscillator.
12. The method of claim 11 , wherein a rate of incrementing the timestamp timer is variable.
13. The method of claim 12 , wherein receiving the synchronization packet further includes gating a media packet based on a gate control signal derived from an output of the timestamp timer.
14. The method of claim 13 , wherein the gate control signal is the output of the timestamp timer.
15. The method of claim 13 , wherein the gate control signal is the output of the timestamp timer added to an offset value.
16. The method of claim 11 , wherein using the synchronization packet reduces jitter between the first and second devices to no more than ±500 ns.
17. An apparatus for wireless communication, comprising:
an oscillator;
a processor;
a memory in electronic communication with the processor; wherein the memory stores instructions that, upon execution by the processor, cause the processor to:
increment a master timestamp timer based on cycles of the oscillator;
generate synchronization packets, each synchronization packet including a timestamp stored by the master timestamp timer and a frame body that consists of information used for synchronization; and
insert each synchronization packet into a stream of data packets for transmission over a wireless network by a synchronization insertion block.
18. The system of claim 17 , wherein the instructions, upon execution by the processor, further cause the processor to:
vary a rate of generating the synchronization packets based on a feedback signal from another device.
19. The system of claim 17 , wherein the stream of data packets for transmission over a wireless network is a real time data stream.
20. The system of claim 17 , wherein the instructions, upon execution by the processor, further cause the processor to:
vary the rate of transmission of synchronization packets based on a feedback signal from another device.
21. The system of claim 17 , wherein the instructions, upon execution by the processor, further cause the processor to:
provide a frame control field that identifies a synchronization packet.
22. The system of claim 17 , wherein the instructions, upon execution by the processor, further cause the processor to:
provide a frame body which includes a timestamp and a sequence number.
23. The system of claim 22 , wherein the timestamp and the sequence number refer to a previously transmitted synchronization packet.
24. The system of claim 22 , wherein the frame body consists of synchronization packets.
25. The system of claim 17 , wherein the instructions, upon execution by the processor, further cause the processor to:
express the timestamp and the sequence number in octets.
26. The system of claim 17 , wherein generating a synchronization packet includes a compilation of a current timestamp and a plurality of previously sent timestamps.
27. The system of claim 26 , wherein the plurality of previously sent timestamps includes the last three timestamps.