IP Library Granted Patent US 10,055,631
Granted Patent B1
US 10,055,631 · App. 15/343,168 · Granted Aug 21, 2018

Semiconductor package for sensor applications

Inventors: Shengmin Wen (Phoenix, AZ); Brett Dunlap (Gilbert, AZ); Jay Kim (Zhubei, TW)
Assignee: Synaptics Incorporated
G06K9/0002H01L23/49816H01L23/5383H01L23/5389H01L24/19H01L24/24H01L2224/2402H01L2224/2413H01L2224/24247H01L2224/24265
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Quick Facts
Patent No.
US 10,055,631
App. No.
15/343,168
Granted
Aug 21, 2018
Kind
B1
Abstract

A sensor package and a method of forming a sensor package are disclosed. The sensor package comprises: a multilayer substrate comprising a mold compound layer and a plurality of patterned metal layers; an embedded die embedded in the multilayer substrate, wherein the mold compound layer of the multilayer substrate surrounds the embedded die; and, a sensing element disposed over the multilayer substrate, the sensing element comprising a first patterned metal layer electrically connected to the embedded die through the multilayer substrate.

Claims (26)

1. A sensor package, comprising:

a multilayer substrate comprising an embedded die, a mold compound layer, and a plurality of patterned metal layers, wherein the embedded die is embedded in the multilayer substrate, and wherein the mold compound layer of the multilayer substrate surrounds the embedded die; and

a sensing element disposed over the multilayer substrate, the sensing element comprising a first patterned metal layer electrically connected to the embedded die through the multilayer substrate wherein the multilayer substrate further comprises a front side facing the sensing element, a back side opposite to the front side, and a plurality of interconnection components disposed on the back side of the multilayer substrate, wherein the plurality of patterned metal layers of the multilayer substrate comprises a second patterned metal layer and a third patterned metal layer, wherein the second patterned metal layer and the third patterned metal layer are disposed on opposing sides of the embedded die, wherein the second patterned metal layer of the multilayer substrate comprises shielding disposed between the embedded die and the sensing element, wherein the shielding is connected to ground or another fixed potential, and wherein the third patterned metal layer comprises a routing trace electrically connected to one of the interconnection components, wherein the one of the interconnection components is disposed within an area overlapping the embedded die.

2. The sensor package of claim 1 , wherein the first patterned metal layer comprises a plurality of capacitive sensing electrodes dimensioned to sense a fingerprint.

3. The sensor package of claim 1 , wherein the sensing element further comprises:

a fourth patterned metal layer electrically connected to the embedded die through the multilayer substrate; and

a thin film dielectric layer disposed between the first patterned metal layer and the fourth patterned metal layer.

4. The sensor package of claim 3 , wherein the first patterned metal layer comprises a plurality of transmitter electrodes and the fourth patterned metal layer comprises a plurality of receiver electrodes.

5. The sensor package of claim 1 , wherein the embedded die comprises a front side and a back side opposite to the front side, wherein the back side of the embedded die faces the sensing element.

6. The sensor package of claim 1 , wherein the embedded die comprises a front side and a back side opposite to the front side, wherein the front side of the embedded die faces the sensing element.

7. The sensor package of claim 6 , wherein the plurality of patterned metal layers of the multilayer substrate comprises a fourth patterned metal layer, wherein the front side of the embedded die is attached to the fourth patterned metal layer with a plurality of die bumps.

8. The sensor package of claim 1 , wherein the sensing element has a lower minimum feature size than the multilayer substrate.

9. The sensor package of claim 8 , wherein the first patterned metal layer of the sensing element has at least one of a lower minimum trace width, a lower minimum trace spacing, and a lower minimum via size than the plurality of patterned metal layers of the multilayer substrate.

10. The sensor package of claim 1 , wherein the plurality of interconnection components comprise at least one of a plurality of solder balls and a plurality of land grid array (LGA) pads.

11. The sensor package of claim 1 , wherein the multilayer substrate comprises a build up layer between the mold compound layer and the sensing element.

12. The sensor package of claim 1 , wherein the multilayer substrate is a laminate substrate.

13. A method of forming a sensor package, the method comprising:

forming a multilayer substrate, wherein the multilayer substrate comprises a mold compound layer and a plurality of patterned metal layers;

providing an embedded die, wherein the embedded die is embedded in the multilayer substrate, wherein the mold compound layer of the multilayer substrate surrounds the embedded die; and

forming a sensing element, wherein the sensing element is disposed over the multilayer substrate, the sensing element comprising a first patterned metal layer electrically connected to the embedded die through the multilayer substrate wherein the multilayer substrate further comprises a front side facing the sensing element, a back side opposite to the front side, and a plurality of interconnection components disposed on the back side of the multilayer substrate, wherein the plurality of patterned metal layers of the multilayer substrate comprises a second patterned metal layer and a third patterned metal layer, wherein the second patterned metal layer and the third patterned metal layer are disposed on opposing sides of the embedded die, wherein the second patterned metal layer of the multilayer substrate comprises shielding disposed between the embedded die and the sensing element, wherein the shielding is connected to ground or another fixed potential, and wherein the third patterned metal layer comprises a routing trace electrically connected to one of the interconnection components, wherein the one of the interconnection components is disposed within an area overlapping the embedded die.

14. The method of claim 13 , wherein the first patterned metal layer comprises a plurality of capacitive sensing electrodes dimensioned to sense a fingerprint.

15. The method of claim 13 , wherein the sensing element further comprises:

a fourth patterned metal layer electrically connected to the embedded die through the multilayer substrate; and

a thin film dielectric layer disposed between the first patterned metal layer and the fourth patterned metal layer.

16. The method of claim 15 , wherein the first patterned metal layer comprises a plurality of transmitter electrodes and the fourth patterned metal layer comprises a plurality of receiver electrodes.

17. The method of claim 13 , wherein the sensing element has a lower minimum feature size than the multilayer substrate.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 051316 FRAME: 0777. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 18, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052186/0756 →
SECURITY INTEREST Recorded Dec 16, 2019
From: SYNAPTICS INCORPROATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051316/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2018
From: DUNLAP, BRETT
To: SYNAPTICS INCORPORATED
Reel/Frame 046294/0776 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2018
From: WEN, SHENGMIN; KIM, JAY
To: SYNAPTICS INCORPORATED
Reel/Frame 046251/0731 →
Continuity (1)
Provisional Application 62250347 · Nov 3, 2015
Cited By (2)
US 12,190,626 US 12,557,675