IP Library Granted Patent US 9,991,274
Granted Patent B2
US 9,991,274 · App. 15/343,591 · Granted Jun 5, 2018

Semiconductor memory device and method for manufacturing the same

Inventor: Naoki Yasuda (Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/1157H01L21/0214H01L21/0223H01L21/02164H01L21/28282H01L27/11565H01L27/11582H01L29/1037H01L29/4234H01L29/511H01L29/518H01L21/02252H01L21/02255
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,991,274
App. No.
15/343,591
Granted
Jun 5, 2018
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

Claims (47)

1. A semiconductor memory device comprising:

a substrate;

a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction above the substrate;

a memory hole that extends in the stacked body in the first direction;

a first insulating member that is disposed to extend in the memory hole in the first direction;

a semiconductor member that is disposed between the stacked body and the first insulating member to extend in the first direction; and

a charge storage member that is disposed between the semiconductor member and one of the plurality of electrode members,

the plurality of electrode members including a first electrode member and a second electrode member,

a diameter of the memory hole at a position of the second electrode member being larger than a diameter of the memory hole at a position of the first electrode member, and

a thickness of the charge storage member at the position of the second electrode member being greater than a thickness of the charge storage member at the position of the first electrode member.

2. The device according to claim 1 , further comprising:

a second insulating member that is disposed between the semiconductor member and the charge storage member,

wherein a thickness of the second insulating member at the position of the first electrode member is greater than a thickness of the second insulating member at the position of the second electrode member.

3. The device according to claim 1 , wherein a distance between the substrate and the first electrode member is less than a distance between the substrate and the second electrode member.

4. The device according to claim 1 , wherein

the plurality of electrode members further include a third electrode member,

a diameter of the memory hole at a position of the third electrode member is larger than the diameter of the memory hole at the position of the second electrode member, and

a thickness of the charge storage member at the position of the third electrode member is greater than a thickness of the charge storage member at the position of the second electrode member.

5. The device according to claim 4 , further comprising:

a second insulating member that is disposed between the semiconductor member and the charge storage member, wherein

a thickness of the second insulating member at the position of the first electrode member is greater than a thickness of the second insulating member at the position of the second electrode member, and

a thickness of the second insulating member at the position of the second electrode member is greater than a thickness of the second insulating member at the position of the third electrode member.

6. The device according to claim 4 , wherein

a distance between the substrate and the first electrode member is less than a distance between the substrate and the second electrode member, and

a distance between the substrate and the second electrode member is less than a distance between the substrate and the third electrode member.

7. The device according to claim 1 , wherein

a diameter of the memory hole becomes gradually smaller from an upper section to a lower section of the stacked body.

8. The device according to claim 2 , wherein

a diameter of the memory hole becomes gradually smaller from an upper section to a lower section of the stacked body, and

a thickness of the second insulating member becomes gradually larger from the upper section to the lower section of the stacked body.

9. The device according to claim 2 , wherein the second insulating member contains silicon oxide.

10. The device according to claim 2 , wherein the second insulating member contains silicon oxynitride.

11. The device according to claim 2 , wherein the second insulating member contains silicon nitride.

12. The device according to claim 2 , wherein the charge storage member contains silicon nitride.

13. The device according to claim 2 , wherein the second insulating member corresponds to a tunnel insulating member.

14. A semiconductor memory device comprising:

a substrate;

a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction above the substrate;

a memory hole that extends in the stacked body in the first direction;

a first insulating member that is disposed to extend in the memory hole in the first direction;

a semiconductor member that is disposed between the stacked body and the first insulating member to extend in the first direction; and

a charge storage member that is disposed between the semiconductor member and one of the plurality of electrode members,

the plurality of electrode members including a first electrode member and a second electrode member,

a width of the memory hole of a second direction perpendicular to the first direction in a plane including the first direction at a position of the second electrode member being larger than a width of the memory hole of the second direction at a position of the first electrode member, and

a thickness of the charge storage member at the position of the second electrode member being greater than a thickness of the charge storage member at the position of the first electrode member.

15. The device according to claim 1 , wherein the thickness of the charge storage member is a thickness of a second direction perpendicular to the first direction.

16. The device according to claim 14 , wherein the thickness of the charge storage member is a thickness of the second direction.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
Continuity (3)
Continuation 14645682 · Mar 12, 2015
Provisional Application 62049226 · Sep 11, 2014
Related Publication 20170077109A1 · Mar 16, 2017