Semiconductor memory device and structure
A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.
1. A semiconductor device, comprising:
a plurality of non-volatile memory cells comprising a first memory cell and a second memory cell,
wherein said plurality of non-volatile memory cells comprises source diffusion lines and drain diffusion lines, at least one of said source diffusion lines and drain diffusion lines are shared by said first memory cell and said second memory cell,
wherein said first memory cell comprises a transistor channel, said transistor channel has two independent facets,
wherein each of said two independent facets comprise at least one independent storage site,
wherein said first memory cell comprises a thin tunneling oxide of less than 1 nm thickness, and
wherein said second memory cell comprises a thick tunneling oxide of greater than 2 nm thickness.
2. The semiconductor device according to claim 1 ,
wherein at least a portion of said memory cells comprises at least one channel facet,
wherein said at least one channel facet is affected by at least two gates to affect at least two storage locations oriented in perpendicular to said at least two gates,
wherein one of said at least two gates is self-aligned to the other of said at least two gates.
3. The semiconductor device according to claim 1 ,
wherein at least one region of one of said drain diffusion lines comprises a junction less transistor (“JLT”).
4. The semiconductor device according to claim 1 ,
wherein a portion of said memory cells comprises at least one channel facet,
wherein said at least one channel facet comprises at least four charge storage locations.
5. The semiconductor device according to claim 1 , further comprising:
a single crystal semiconductor layer overlaying said memory cells; and
through silicon vias,
wherein said through silicon vias have a radius less than 250 nm.
6. The semiconductor device according to claim 1 ,
wherein said first memory cell and said second memory cell additionally function as volatile floating body memory cells.
7. The semiconductor device according to claim 1 , further comprising:
a plurality of volatile memory cells; and
a controller,
wherein said controller is designed to operate a direct transfer of data from a portion of said non-volatile memory cells to a portion of said volatile memory cells.
8. A semiconductor device, comprising:
a plurality of non-volatile memory cells comprising a first memory cell and a second memory cell,
wherein said plurality of non-volatile memory cells comprises source diffusion lines and drain diffusion lines, at least one of said source diffusion lines and drain diffusion lines are shared by said first memory cell and said second memory cell,
wherein said first memory cell comprises a transistor channel, said transistor channel has two independent facets,
wherein each of said two independent facets comprise at least one independent storage site,
wherein at least one region of one of said drain diffusion lines comprises a junction less transistor (“JLT”).
9. The semiconductor device according to claim 8 ,
wherein at least a portion of said memory cells comprises at least one channel facet,
wherein said at least one channel facet is affected by at least two gates to affect at least two storage locations oriented in perpendicular to said at least two gates,
wherein one of said at least two gates is self-aligned to the other of said at least two gates.
10. The semiconductor device according to claim 8 ,
wherein said first memory cell comprises a thin tunneling oxide of less than 1 nm thickness, and
wherein said second memory cell comprises a thick tunneling oxide of greater than 2 nm thickness.
11. The semiconductor device according to claim 8 ,
wherein a portion of said memory cells comprises at least one channel facet,
wherein said at least one channel facet comprises at least four charge storage locations.
12. The semiconductor device according to claim 8 , further comprising:
a single crystal semiconductor layer overlaying said memory cells; and
through silicon vias,
wherein said through silicon vias have a radius less than 250 nm.
13. The semiconductor device according to claim 8 ,
wherein said first memory cell comprises a transistor channel, said transistor channel has two independent facets,
wherein each of said two independent facets comprise at least one independent storage site.
14. The semiconductor device according to claim 8 , further comprising:
a plurality of volatile memory cells; and
a controller,
wherein said controller is designed to operate a direct transfer of data from a portion of said non-volatile memory cells to a portion of said volatile memory cell.
15. A semiconductor device, comprising:
a plurality of non-volatile memory cells comprising a first memory cell and a second memory cell,
wherein said plurality of non-volatile memory cells comprises source diffusion lines and drain diffusion lines, at least one of said source diffusion lines and drain diffusion lines are shared by said first memory cell and said second memory cell,
wherein said first memory cell comprises a transistor channel said transistor channel has two independent facets,
wherein each of said two independent facets comprise at least one independent storage site,
wherein at least one region of one of said drain diffusion lines comprises a junction less transistor (“JLT”).
16. A semiconductor device, comprising:
a plurality of non-volatile memory cells comprising a first memory cell and a second memory cell,
wherein said plurality of non-volatile memory cells comprises source diffusion lines and drain diffusion lines, at least one of said source diffusion lines and drain diffusion lines are shared by said first memory cell and said second memory cell,
wherein said first memory cell comprises a transistor channel, said transistor channel has two independent facets,
wherein each of said two independent facets comprise at least one independent storage site,
wherein said first memory cell comprises a thin tunneling oxide of less than 1 nm thickness, and
wherein said second memory cell comprises a thick tunneling oxide of greater than 2 nm thickness.
17. A semiconductor device, comprising:
a plurality of non-volatile memory cells comprising a first memory cell and a second memory cell,
wherein said plurality of non-volatile memory cells comprises source diffusion lines and drain diffusion lines, at least one of said source diffusion lines and drain diffusion lines are shared by said first memory cell and said second memory cell,
wherein said first memory cell comprises a transistor channel said transistor channel has two independent facets,
wherein each of said two independent facets comprise at least one independent storage site,
wherein at least a portion of said memory cells comprises at least one channel facet,
wherein said at least one channel facet is affected by at least two gates to affect at least two storage locations oriented in perpendicular to said at least two gates,
wherein one of said at least two gates is self-aligned to the other of said at least two gates.