SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first region including first memory cells and first wiring layers, and a second region including second memory cells and second wiring layers, the first and second wiring layers each including a first level wiring layer and a second level wiring layer. End portions of the first and second wiring layers extend in a first direction into a wiring pullout region, such that each of the first and second level wiring layers has an exposed upper surface. The exposed upper surfaces of the first and second level wiring layers are adjacent in a second direction crossing the first direction. First and second contacts are arranged respectively on the exposed surfaces of the first and second level wiring layers, such that the first contacts and the second contacts are arranged respectively along first and second lines extending in the first direction
1 . A semiconductor memory device comprising:
a memory cell array that includes a first region including a plurality of first memory cells and a plurality of first wiring layers stacked over a semiconductor substrate, and a second region including a plurality of second memory cells and a plurality of second wiring layers stacked over the semiconductor substrate, the first and second wiring layers each including a wiring layer at a first level above the substrate and a wiring layer at a second level above the substrate, wherein
end portions of each of the first wiring layers and the second wiring layers extend in a first direction into a wiring pullout region, such that each of the first and second level wiring layers of both the first and second wiring layers has an exposed upper surface, and
in each of the first wiring layers and the second wiring layers, the exposed upper surfaces of the first and second level wiring layers are adjacent in a second direction crossing the first direction; and
first and second contacts arranged respectively on the exposed surfaces of the first and second level wiring layers of each of the first and second wiring layers, such that the first contacts and the second contacts are arranged respectively along first and second lines that extend in the second direction and are spaced apart in the first direction.
2 . The device according to claim 1 , further comprising:
a first conductive line coupled to the first contacts and extending in the second direction; and
a second conductive line coupled to the second contacts and extending in the second direction.
3 . The device according to claim 2 , wherein the first and second conductive lines are at a same level above the substrate.
4 . The device according to claim 1 , wherein
the first and second wiring layers each further include a wiring layer at a third level above the substrate and a wiring layer at a fourth level above the substrate, end portions of each of the first wiring layers and the second wiring layers extending in the first direction into the wiring pullout region, such that each of the third and fourth level wiring layers of both the first and second wiring layers has an exposed upper surface, and
in each of the first wiring layers and the second wiring layers, the exposed upper surfaces of the third and fourth level wiring layers are adjacent in the second direction, and the exposed upper surfaces of the first and third level wiring layers are adjacent and the exposed upper surfaces of the second and fourth level wiring layers are adjacent, in the first direction.
5 . The device according to claim 4 , further comprising:
a third contact arranged on the exposed surface of the third level wiring layer of each of the first and second wiring layers; and
a fourth contact arranged on the exposed surface of the fourth level wiring layer of each of the first and second wiring layers, wherein
the third contacts and the fourth contacts are arranged respectively along third and fourth lines that extend in the second direction and are spaced apart in the first direction.
6 . The device according to claim 5 , wherein the memory cell array further includes:
a third region including a plurality of third memory cells and a plurality of third wiring layers stacked over the semiconductor substrate, the third wiring layer including wiring layers at the first, second, third, and fourth levels above the substrate, end portions of third wiring layers extending in the first direction into the wiring pullout region, such that each of the first, second, third, and fourth level wiring layers of the third wiring layers has an exposed upper surface;
a fourth region including a plurality of fourth memory cells and a plurality of fourth wiring layers stacked over the semiconductor substrate, the fourth wiring layer including wiring layers at the first, second, third, and fourth levels above the substrate, end portions of fourth wiring layers extending in the first direction into the wiring pullout region, such that each of the first, second, third, and fourth level wiring layers of the fourth wiring layers has an exposed upper surface, wherein
in each of the third wiring layers and the fourth wiring layers, the exposed upper surfaces of the third and fourth level wiring layers are adjacent in the second direction, and the exposed upper surfaces of the first and third level wiring layers are adjacent and the exposed upper surfaces of the second and fourth level wiring layers are adjacent, in the first direction.
7 . The device according to claim 6 , further comprising:
first and second contacts arranged respectively on the exposed surfaces of the first and second level wiring layers of each of the third and fourth wiring layers, such that the first contacts and the second contacts are arranged respectively along the first and second lines; and
third and fourth contacts arranged respectively on the exposed surfaces of the third and fourth level wiring layers of each of the third and fourth wiring layers, such that the third contacts and the fourth contacts are arranged respectively along the third and fourth lines.
8 . The device according to claim 5 , wherein
in each of the first wiring layers and the second wiring layers, the second level wiring layer is stacked above and the first level wiring layer, the third level wiring layer above the second level wiring layer, and the fourth level wiring layer above the third level wiring layer.
9 . The device according to claim 1 , further comprising:
a planar contact on the substrate that extends above the substrate and in the first direction to separate the first region and the second region.
10 . The device according to claim 1 , further comprising:
a planar contact on the substrate that extends above the substrate and in the first direction to separate the first region and the second region.
11 . The device according to claim 1 , wherein
each of the first and second wiring layers includes a first select gate line, a plurality of word lines above the first select gate line, and a second select gate line above the word lines, and
the first, second, third, and fourth level wiring layers are each one of the word lines.
12 . The device according to claim 11 , wherein the memory cell array further includes:
a plurality of third memory cells that share the word lines of the first wiring layers with the first memory cells;
a plurality of fourth memory cells that share the word lines of the second wiring layers with the second memory cells;
first, second, third, and fourth select transistors for selecting the first, second, third, and fourth memory cells, respectively; and
first, second, third, and fourth select gate lines coupled to gates of the first, second, third, and fourth select transistors, respectively, wherein
one of the first wiring layers is separated into the first and second select gate lines that are electrically insulated from each other, and one of the second wiring layers is separated into the third and fourth select gate lines that are electrically insulated from each other.
13 . A semiconductor memory device comprising:
a memory cell array that includes a first region including a plurality of first memory cells and a plurality of first wiring layers stacked over a semiconductor substrate, and a second region including a plurality of second memory cells and a plurality of second wiring layers stacked over the semiconductor substrate, the first and second wiring layers each including a wiring layer at a first level above the substrate, a wiring layer at a second level above the substrate, and a wiring layer at a third level above the substrate, wherein
end portions of each of the first wiring layers and the second wiring layers extend in a first direction into a wiring pullout region, such that each of the first, second, and third level wiring layers of both the first and second wiring layers has an exposed upper surface, and
in each of the first wiring layers and the second wiring layers, the exposed upper surfaces of the first, second, and third level wiring layers are adjacent in a second direction crossing the first direction; and
first, second, and third contacts arranged respectively on the exposed surfaces of the first, second, and third level wiring layers of each of the first and second wiring layers, such that the first contacts, the second contacts, and the third contacts are arranged respectively along first, second, and third lines that extend in the second direction and are spaced apart from each other in the first direction.
14 . The device according to claim 13 , further comprising:
a first conductive line coupled to the first contacts and extending in the second direction;
a second conductive line coupled to the second contacts and extending in the second direction; and
a third conductive line coupled to the third contacts and extending in the second direction.
15 . The device according to claim 14 , wherein the first, second, and third conductive lines are at a same level above the substrate.
16 . The device according to claim 13 , wherein
in each of the first wiring layers and the second wiring layers, the second level wiring layer is stacked above and the first level wiring layer and the third level wiring layer is stacked above the second level wiring layer.
17 . A semiconductor memory device comprising:
a memory cell array that includes a first region including a plurality of first memory cells and a plurality of first wiring layers stacked over a semiconductor substrate, and a second region including a plurality of second memory cells and a plurality of second wiring layers stacked over the semiconductor substrate, the first and second wiring layers each including a wiring layer at a first level above the substrate, a wiring layer at a second level above the substrate, a wiring layer at a third level above the substrate, and a wiring layer at a fourth level above the substrate, wherein
end portions of each of the first wiring layers and the second wiring layers extend in a first direction into a wiring pullout region, such that each of the first, second, third, and fourth level wiring layers of both the first and second wiring layers has an exposed upper surface, and
in each of the first wiring layers and the second wiring layers, the exposed upper surfaces of the first, second, third, and fourth level wiring layers are adjacent in a second direction crossing the first direction; and
first, second, third, and fourth contacts arranged respectively on the exposed surfaces of the first, second, third, and fourth level wiring layers of each of the first and second wiring layers, such that the first contacts, the second contacts, the third contacts, and the fourth contacts are arranged respectively along first, second, third, and fourth lines that extend in the second direction and are spaced apart from each other in the first direction.
18 . The device according to claim 17 , further comprising:
a first conductive line coupled to the first contacts and extending in the second direction;
a second conductive line coupled to the second contacts and extending in the second direction;
a third conductive line coupled to the third contacts and extending in the second direction; and.
a fourth conductive line coupled to the fourth contacts and extending in the second direction.
19 . The device according to claim 18 , wherein the first, second, third, and fourth conductive lines are at a same level above the substrate.
20 . The device according to claim 17 , wherein
in each of the first wiring layers and the second wiring layers, the second level wiring layer is stacked above and the first level wiring layer, the third level wiring layer above the second level wiring layer, and the fourth level wiring layer above the third level wiring layer.