Method and apparatus for exchanging data between devices operating at different clock rates
Source-synchronous communications between networked devices can be hindered by differing clock rates and data interface formats among the devices. By implementing a plurality of clock converters, a data interface format of a transmitting device is converted to a data interface format compatible with a receiving device. The clock converters provide a clock signal based on the source-synchronous data clock, and having a phase controlled with respect to an associated data signal. As a result, data exchange between devices operating at different clock rates is made possible.
1. An apparatus for converting a data interface format to enable data exchange between devices operating at different clock rates, the apparatus comprising:
a clock up-converter configured to derive an up-converted clock signal from a first clock signal at a first clock rate of a first device and to transmit the up-converted clock signal to a second device, the up-converted clock signal having a phase controlled with respect to a phase of an associated first data signal;
a clock down-converter configured to derive a down-converted clock signal from a second clock signal at a second clock rate of the second device to transmit the down-converted clock signal to the first device, the down-converted clock signal having a phase controlled with respect to a phase of an associated second data signal, the second clock rate being different from the first clock rate; and
a controller configured to control a multiplexer at each of the first and second devices to 1) in a first mode, output a data signal to a respective data bus, and 2) in a second mode, output an alignment pattern to the respective data bus, the controller being further configured to generate control signals to control the respective phases of the up-converted and down-converted clock signals based on relative phases of the first and second clock signals with respect to the associated first and second data signals.
2. The apparatus of claim 1 , wherein each of the clock up-converter and the clock down-converter employs a phase-locked loop (PLL).
3. The apparatus of claim 2 , wherein the PLL employed by the clock up-converter includes a multiplier and the PLL employed by the clock down-converter includes a divider.
4. The apparatus of claim 1 , wherein the controller is further configured to cause the first and second devices to transmit alignment patterns.
5. The apparatus of claim 4 , where in the controller is further configured to adjust phases of the up-converted and down-converted clock signals as a function of the alignment patterns.
6. The apparatus of claim 4 , wherein the controller is further configured to align the up-converted and down-converted clock signals with the associated first and second data signals as a function of the alignment patterns.
7. The apparatus of claim 1 , wherein the controller is further configured to align the up-converted and down-converted clock signals with the associated first and second data signals at startup of the first and second devices.
8. The apparatus of claim 1 , wherein the controller is further configured to control the multiplexer to transition between the first and second modes based on an error signal associated with the alignment pattern.
9. A method of converting a data interface format to enable data exchange between devices operating at different clock rates, the method comprising:
up-converting a first clock signal at a first clock rate from a first device to an up-converted clock signal, the up-converted clock signal having a phase controlled with respect to a phase of an associated first data signal;
down-converting a second clock signal at a second clock rate from a second device to a down-converted clock signal, the down-converted clock signal having a phase controlled with respect to a phase of an associated second data signal, the second clock rate being different from the first clock rate;
transmitting the up-converted and down-converted clock signals respectively to the second and first devices;
controlling a multiplexer at each of the first and second devices to 1) in a first mode, output a data signal to a respective data bus, and 2) in a second mode, output an alignment pattern to the respective data bus; and
generating control signals to control the respective phases of the up-converted and down-converted clock signals based on relative phases of the first and second clock signals with respect to the associated first and second data signals.
10. The method of claim 9 , wherein the up-converting and the down-converting include controlling a phase-locked loop (PLL).
11. The method of claim 10 , wherein up-converting the first clock signal includes multiplying the first clock signal, and down-converting the second clock signal includes dividing the second clock signal.
12. The method of claim 9 , further comprising causing the first and second devices to transmit alignment patterns.
13. The method of claim 12 , further comprising adjusting phases of the derived up-converted and down-converted clock signals as a function of the alignment patterns.
14. The method of claim 12 , further comprising aligning the up-converted and down-converted clock signals with the associated first and second data signals as a function of the alignment patterns.
15. The method of claim 9 , further comprising aligning the up-converted and down-converted clock signals with the associated first and second data signals at startup of the first and second devices.
16. The method of claim 9 , further comprising controlling the multiplexer to transition between the first and second modes based on an error signal associated with the alignment pattern.